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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269802df446sm117628455ad.68.2025.09.21.20.23.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 21 Sep 2025 20:23:47 -0700 (PDT) Message-ID: Date: Mon, 22 Sep 2025 11:23:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 14/14] drm/msm/dp: Add support for lane mapping configuration To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250919-add-displayport-support-for-qcs615-platform-v5-0-eae6681f4002@oss.qualcomm.com> <20250919-add-displayport-support-for-qcs615-platform-v5-14-eae6681f4002@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzMiBTYWx0ZWRfX6yUn5BQ+Et72 qvEYl82ktDGVLoeiy2rNRHNDG779yYePY9uI6P7y51Y8JfhpT97nJyUflm/BGEyYN6i4Wd+DcNF jLhMyQY4pv4bkM437i6ohgEuRzEpZ3FWtwAY3VluWPGcedYelUmT5+oGwVj49ExdrfbxXSyTfmH ecx+rY/QcLifTRCGbjPKBZYa4y23fteRvvtWKaRYOc9ia5Afjq8ciPXfw6fE1M5FQV1ougQq83v tkMGYS23SDmjpKd8mhJFp/F3k3QQBBjM1GoNsPhw+WKXPf/Di8bUzpsKS2xnPFenSiSV5SlmOSh /QJ1Mfh9i5h5Vd0FxXG78xSN5VU/xdm/fx4poDxXe90tJ6lGnFWFdK8yacx1YVxJdBUW8nPpksx nMzcoRs4 X-Proofpoint-GUID: PssfMBWt68nKpHjuSh-n8Gg--fCLuh0I X-Authority-Analysis: v=2.4 cv=UvtjN/wB c=1 sm=1 tr=0 ts=68d0c145 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=z90s4CAT84tkWkAwxOgA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: PssfMBWt68nKpHjuSh-n8Gg--fCLuh0I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-21_10,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200032 On 9/20/2025 2:35 AM, Dmitry Baryshkov wrote: > On Fri, Sep 19, 2025 at 10:24:31PM +0800, Xiangxu Yin wrote: >> QCS615 platform requires non-default logical-to-physical lane mapping due >> to its unique hardware routing. Unlike the standard mapping sequence >> <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit >> configuration via the data-lanes property in the device tree. This ensures >> correct signal routing between the DP controller and PHY. >> >> For partial definitions, fill remaining lanes with unused physical lanes >> in ascending order. >> >> Signed-off-by: Xiangxu Yin >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++---- >> drivers/gpu/drm/msm/dp/dp_link.c | 60 ++++++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/dp/dp_link.h | 1 + >> 3 files changed, 66 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c >> index 2aeb3ecf76fab2ee6a9512b785ca5dceebfc3964..34a91e194a124ef5372f13352f7b3513aa88da2a 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_link.c >> +++ b/drivers/gpu/drm/msm/dp/dp_link.c >> @@ -1236,6 +1236,61 @@ static u32 msm_dp_link_link_frequencies(struct device_node *of_node) >> return frequency; >> } >> >> +/* >> + * Always populate msm_dp_link->lane_map with 4 lanes. >> + * - Use DTS "data-lanes" if present; otherwise fall back to default mapping. >> + * - For partial definitions, fill remaining entries with unused lanes in >> + * ascending order. >> + */ >> +static int msm_dp_link_lane_map(struct device *dev, struct msm_dp_link *msm_dp_link) >> +{ >> + struct device_node *of_node = dev->of_node; >> + struct device_node *endpoint; >> + int cnt = msm_dp_link->max_dp_lanes; >> + u32 tmp[DP_MAX_NUM_DP_LANES]; >> + u32 map[DP_MAX_NUM_DP_LANES] = {0, 1, 2, 3}; /* default 1:1 mapping */ >> + bool used[DP_MAX_NUM_DP_LANES] = {false}; >> + int i, j = 0, ret = -EINVAL; >> + >> + endpoint = of_graph_get_endpoint_by_regs(of_node, 1, -1); >> + if (endpoint) { >> + ret = of_property_read_u32_array(endpoint, "data-lanes", tmp, cnt); >> + if (ret) >> + dev_dbg(dev, "endpoint data-lanes read failed (ret=%d)\n", ret); >> + } >> + >> + if (ret) { >> + ret = of_property_read_u32_array(of_node, "data-lanes", tmp, cnt); >> + if (ret) { >> + dev_info(dev, "data-lanes not defined, set to default\n"); >> + goto out; >> + } >> + } >> + >> + for (i = 0; i < cnt; i++) { >> + if (tmp[i] >= DP_MAX_NUM_DP_LANES) { >> + dev_err(dev, "data-lanes[%d]=%u out of range\n", i, tmp[i]); >> + return -EINVAL; >> + } >> + used[tmp[i]] = true; >> + map[i] = tmp[i]; >> + } >> + >> + /* Fill the remaining entries with unused physical lanes (ascending) */ >> + for (i = cnt; i < DP_MAX_NUM_DP_LANES && j < DP_MAX_NUM_DP_LANES; j++) { > Nit: i = cnt, j = 0; Don't init loop variables at the top of the > function. > > Other than that: > > Reviewed-by: Dmitry Baryshkov > Ack. >> + if (!used[j]) >> + map[i++] = j; >> + } >> + >> +out: >> + if (endpoint) >> + of_node_put(endpoint); >> + >> + dev_dbg(dev, "data-lanes count %d <%d %d %d %d>\n", cnt, map[0], map[1], map[2], map[3]); >> + memcpy(msm_dp_link->lane_map, map, sizeof(map)); >> + return 0; >> +} >> + >> static int msm_dp_link_parse_dt(struct device *dev, struct msm_dp_link *msm_dp_link) >> { >> struct device_node *of_node = dev->of_node;