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Peter Anvin" , Andrew Cooper , Mikhail Paulyshka , Kai Huang References: <20260603063317.13665-1-kprateek.nayak@amd.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002315:EE_|DS0PR12MB6461:EE_ X-MS-Office365-Filtering-Correlation-Id: c742acfd-d442-4ee8-3821-08dec2b755d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|82310400026|1800799024|13003099007|921020|22082099003|4143699003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: J35p+ujezqw4bQdJsh+ghadjqHPGLAXpj2Wsb6V/somtiRMYjxKIvHAjCsTbCKorX+zW2hrzo6u5L5MLh12qhYi2nuoXeW14HJF1FvlQIFozEGacFtqu5ZRNZLxiBW5PQFTdOl4dGQ7Z23fAcb3v/nuv+pyR+Cd/sU8E/4/XTSC3Rgc+bOAZgCiwq8/TIGbxFU2Qzqb8wUOEWQP0DKYL2IRK3iDj+Wh8ZOj90riX5mTAWUqUJeh93eggd6A3vlIwtCDdPDMYlf8jLX+wxfF4TEvPIjH+jVdQMP0EopqiA7dGC6YPee5abS9wPWUhuDE+ZN4nQTY+8lt75RzA3qfcxvMc7lQxmHYciz+swkrlJs+6V46KvIf/Lh4pmoD+3UTOXjyk2uRt1pII0j2pe162uj6nI1mVqnlAO37rjHSreDC1M/z7+kDBssSWQ3rdMEKTclkaWNJ/RAUgdMrcc8k5DZCbtNkTIGutBxeRIbBqPcHcvcJLiOckcx87/SsGEcUK2vjDhGeKVKzyLix457/db3AngYyow/2xctjZe1n77+csct3tGO80jXAmwDz+lAYjg/LOgNoewQns7IpyQw1TnSDdU7vhIOdbFzWTsS/OgquSmKBifSOP9t50ATJSbhUktqQeSd4I0Q3g1dqkUY34LvB+jgAkdIpAEOpVSSJf6XiiWQnhSt9WT2LhtL67w7GjuIwY81j6ol8+a4Xs9p5lDSbtXs9qzVE6zXTjih4oUJNar/0F7WuhWeLlka3c+CxNpuYJwn/yhrVba6r+xjjpI8SRfYFQI4oeNVCHOYtT7Dw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(82310400026)(1800799024)(13003099007)(921020)(22082099003)(4143699003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iKiz8Co0VMswrubA9dEYYVB735eg2BlzVe6IDiGY1tik8J2fhcV9Syb4YzEkNrGtRmuwb/i1ZEQaL4L0XN/g99gtuKHglvoTWR9cJGG3H6OYGQmvJ75JxF6/JA/at8zI+KPsrC7KoasCJL8qF2LK8OLGyJD+sxv8VyvtmXG+XbXrRhtGBWJgJNsTdD94vSo9dFHCRVD1728BsR/KlaLminy+B/MVwRGEU2M70lFHi11dHFAfDBWr+yNYlW6VFm6ZB6QZ6N/EI25KZFJmIpvirLJXUaEr1hgDNmA0Q0oq+5c8cvHW9UC5Jb2ODPIC05QcfxE6vYDuq5C2YnjCKM8OqeSzHQ3bHUqRs9bKaYD7hXe29Q2sF4GjcS//lRJUKbfmCwKkvPYGxXCgpP4p+CaQbN1mb1vE/TZOlTnKdMh8IAuJdFS3yhMvwt1lcahBZ+mA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 04:03:00.7000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c742acfd-d442-4ee8-3821-08dec2b755d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002315.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6461 Hello Rong, On 6/3/2026 8:07 PM, Rong Zhang wrote: >> Since these records are read-only, the status cannot be cleared once >> consumed and the last reset reason will persist across kxec until next >> reset which reintroduces the case prevented by commit e6416c2dfe23c >> ("x86/CPU/AMD: Prevent reset reasons from being retained across reboot") >> by clearing the FCH register once consumed. > > It's not only about kexec. > > The last reset reason register could remain unchanged when the reset is > caused by a voltage drop on a power rail, probably due to a broken power > supply or VRM. This wasted me a lot of frustrating time debugging > irrelevant reset reasons. > > Eventually, I RMA'd the broken device and submitted the patch to save > other's time. > > Also, some bits are not cleared by hardware as per [1]. If the firmware > doesn't clear them either they will persist anyway. > > So I'd prefer clearing the register in any cases. > > [1]: https://bugzilla.kernel.org/show_bug.cgi?id=206537#attach_303991 Thanks a ton for the additional context. I'm checking with the BIOS folks if this PHAT record behaves any differently or if it just mirrors the FCH::PM::S5_RESET_STATUS at the time the firmware loads. If it is the latter, yes, I agree with you that we need to clear the FCH register regardless. I'll adjust the v2 accordingly based on what the BIOS folks come back with. -- Thanks and Regards, Prateek