From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D89F1318EC9 for ; Tue, 31 Mar 2026 21:13:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774991583; cv=none; b=RBfRRCFXMHmuRzTb/UXK3mM77tZwSnB/8ughTwedUjGvIXw/Kdh/I8sER3nLvPwiTHCQgFqZaaeZ8UzoOISjA+DGgwvd0zZdMzzB3duCEZEyWh62/paqby7GSlkZwL5AT2BWBXqLdVa2IV/lUW/wU+F+pgc+7C3jf6SVCo5oUgc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774991583; c=relaxed/simple; bh=ZJcXdzYVKjza+0B4ij2cCWOffJbZC6efFzBimXxuFXI=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=CIHCL1nHkF8ick+dGnogq7qlWJ2oFgA9NtoIQ6MEL2AqJfz7QkumzZ2wLKd41swfvYqDcMM1ooTD/EFfIdNP9iTvoI9QZvuIxyaYOAO1Ln+5yUCCmK0S827oKjxofR/DNfZC83E1tOchxAmwP9b9SvQlOgSzK89/D8GKyaiXcrk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=XvipFfy7; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="XvipFfy7" Received: from dog.kanata.rendec.net (pool-174-112-193-187.cpe.net.cable.rogers.com [174.112.193.187]) by mail.mindbit.ro (Postfix) with ESMTPSA id 7A216C24F8; Wed, 1 Apr 2026 00:12:50 +0300 (EEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro 7A216C24F8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1774991571; bh=VpY/Jjx1EpV6W5tmSmvNZ2UOu7nwPcMD4Deq3M6QRsI=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=XvipFfy7RWPwPmD3sok2neIhaqn/hVEdFezt9JRKIhSItWpDwyUEcXSi9GJ4uN8eV 6IKCLgqgw5rYEBVKVSrCrglwVLJj+tH01B9HgCNd2yF2WISkY531S2TtUkIzab9PAa Klw/R45eIszd9HkiBvVh7qdo9iwp6yqZCqU4ExACEmHG0/umHLIul8TlzDFxkAkqag zMv5RNcfkiP+Erh93Oo7YWS3IuKXC2cX+hm3vBZAGhaDKCXJ/kEdCCM8fD0SCAU2NL 3ZRE/5JlDzfWGDynXdXFGpOfUPb4sgvAeF6WfxtNCPX+gAdFxNIZ3nr3W6CGtUtN2i Ui5Soy0cTUMbg== Message-ID: Subject: Re: [patch V4 05/15] x86/irq: Suppress unlikely interrupt stats by default From: Radu Rendec To: Thomas Gleixner , LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Date: Tue, 31 Mar 2026 17:12:48 -0400 In-Reply-To: <20260331072418.880584661@kernel.org> References: <20260331071453.172185305@kernel.org> <20260331072418.880584661@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-03-31 at 09:25 +0200, Thomas Gleixner wrote: > From: Thomas Gleixner >=20 > Unlikely interrupt counters like the spurious vector and the synthetic AP= IC > ICR read retry show up in /proc/interrupts with all counts 0 most of the > time. >=20 > As these are events which should never happen, suppress them by default a= nd > enable them for output when they actually happen. >=20 > This requires a seperate bitmap as the description array is marked > __ro_after_init. With that bitmap in place it becomes RO data. >=20 > Signed-off-by: Thomas Gleixner > --- > V4: Fix the bad idea of writing to __ro_after_init marked data > V3: New patch > --- > =C2=A0arch/x86/include/asm/hardirq.h |=C2=A0=C2=A0=C2=A0 1 + > =C2=A0arch/x86/kernel/apic/apic.c=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 2= +- > =C2=A0arch/x86/kernel/apic/ipi.c=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2= =A0 2 +- > =C2=A0arch/x86/kernel/irq.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 28 ++++++++++++++++++---------- > =C2=A04 files changed, 21 insertions(+), 12 deletions(-) > --- a/arch/x86/include/asm/hardirq.h > +++ b/arch/x86/include/asm/hardirq.h > @@ -68,6 +68,7 @@ DECLARE_PER_CPU_ALIGNED(struct pi_desc, > =C2=A0#define __ARCH_IRQ_STAT > =C2=A0 > =C2=A0#define inc_irq_stat(index) this_cpu_inc(irq_stat.counts[IRQ_COUNT_= ##index]) > +void irq_stat_inc_and_enable(enum irq_stat_counts which); This is just a matter of style but for symmetry with inc_irq_stat(), I would prepend '__' to the function name and create a wrapper macro that adds the 'IRQ_COUNT_' prefix. And for consistency (you also have inc_perf_irq_stat()) I would call it inc_and_enable_irq_stat(). And yes, my comments above are totally bike shedding :) > =C2=A0#ifdef CONFIG_X86_LOCAL_APIC > =C2=A0#define inc_perf_irq_stat() inc_irq_stat(APIC_PERF) > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -2108,7 +2108,7 @@ static noinline void handle_spurious_int > =C2=A0 > =C2=A0 trace_spurious_apic_entry(vector); > =C2=A0 > - inc_irq_stat(SPURIOUS); > + irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS); > =C2=A0 > =C2=A0 /* > =C2=A0 * If this is a spurious interrupt then do not acknowledge > --- a/arch/x86/kernel/apic/ipi.c > +++ b/arch/x86/kernel/apic/ipi.c > @@ -120,7 +120,7 @@ u32 apic_mem_wait_icr_idle_timeout(void) > =C2=A0 for (cnt =3D 0; cnt < 1000; cnt++) { > =C2=A0 if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) > =C2=A0 return 0; > - inc_irq_stat(ICR_READ_RETRY); > + irq_stat_inc_and_enable(IRQ_COUNT_ICR_READ_RETRY); > =C2=A0 udelay(100); > =C2=A0 } > =C2=A0 return APIC_ICR_BUSY; > --- a/arch/x86/kernel/irq.c > +++ b/arch/x86/kernel/irq.c > @@ -68,19 +68,24 @@ struct irq_stat_info { > =C2=A0 const char *text; > =C2=A0}; > =C2=A0 > +#define DEFAULT_SUPPRESSED_VECTOR UINT_MAX > + > =C2=A0#define ISS(idx, sym, txt) [IRQ_COUNT_##idx] =3D { .symbol =3D sym,= .text =3D txt } > =C2=A0 > =C2=A0#define ITS(idx, sym, txt) [IRQ_COUNT_##idx] =3D \ > =C2=A0 { .skip_vector =3D idx## _VECTOR, .symbol =3D sym, .text =3D txt } > =C2=A0 > -static struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] __ro_after_init= =3D { > +#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] =3D \ > + { .skip_vector =3D DEFAULT_SUPPRESSED_VECTOR, .symbol =3D sym, .text = =3D txt } > + > +static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] =3D { > =C2=A0 ISS(NMI, "NMI", "=C2=A0 Non-maskable interrupts\n"), > =C2=A0#ifdef CONFIG_X86_LOCAL_APIC > =C2=A0 ISS(APIC_TIMER, "LOC", "=C2=A0 Local timer interrupts\n"), > - ISS(SPURIOUS, "SPU", "=C2=A0 Spurious interrupts\n"), > + IDS(SPURIOUS, "SPU", "=C2=A0 Spurious interrupts\n"), > =C2=A0 ISS(APIC_PERF, "PMI", "=C2=A0 Performance monitoring interrupts\= n"), > =C2=A0 ISS(IRQ_WORK, "IWI", "=C2=A0 IRQ work interrupts\n"), > - ISS(ICR_READ_RETRY, "RTR", "=C2=A0 APIC ICR read retries\n"), > + IDS(ICR_READ_RETRY, "RTR", "=C2=A0 APIC ICR read retries\n"), > =C2=A0 ISS(X86_PLATFORM_IPI, "PLT", "=C2=A0 Platform interrupts\n"), > =C2=A0#endif > =C2=A0#ifdef CONFIG_SMP > @@ -121,29 +126,32 @@ static struct irq_stat_info irq_stat_inf > =C2=A0#endif > =C2=A0}; > =C2=A0 > +static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly; > + > =C2=A0static int __init irq_init_stats(void) > =C2=A0{ > - struct irq_stat_info *info =3D irq_stat_info; > + const struct irq_stat_info *info =3D irq_stat_info; > =C2=A0 > =C2=A0 for (unsigned int i =3D 0; i < ARRAY_SIZE(irq_stat_info); i++, inf= o++) { > - if (info->skip_vector && test_bit(info->skip_vector, system_vectors)) > - info->skip_vector =3D 0; > + if (!info->skip_vector || (info->skip_vector !=3D DEFAULT_SUPPRESSED_V= ECTOR && > + =C2=A0=C2=A0 test_bit(info->skip_vector, system_vectors))) > + set_bit(i, irq_stat_count_show); > =C2=A0 } > =C2=A0 > =C2=A0#ifdef CONFIG_X86_LOCAL_APIC > =C2=A0 if (!x86_platform_ipi_callback) > - irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector =3D 1; > + clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show); > =C2=A0#endif > =C2=A0 > =C2=A0#ifdef CONFIG_X86_POSTED_MSI > =C2=A0 if (!posted_msi_enabled()) > - irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector =3D 1; > + clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show); > =C2=A0#endif > =C2=A0 > =C2=A0#ifdef CONFIG_X86_MCE_AMD > =C2=A0 if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && > =C2=A0 =C2=A0=C2=A0=C2=A0 boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) > - irq_stat_info[IRQ_COUNT_DEFERRED_VECTOR].skip_vector =3D 1; > + clear_bit(IRQ_COUNT_DEFERRED_ERROR, irq_stat_count_show); > =C2=A0#endif > =C2=A0 return 0; > =C2=A0} > @@ -168,7 +176,7 @@ int arch_show_interrupts(struct seq_file > =C2=A0 const struct irq_stat_info *info =3D irq_stat_info; > =C2=A0 > =C2=A0 for (unsigned int i =3D 0; i < ARRAY_SIZE(irq_stat_info); i++, inf= o++) { > - if (info->skip_vector) > + if (!test_bit(i, irq_stat_count_show)) > =C2=A0 continue; > =C2=A0 > =C2=A0 seq_printf(p, "%*s:", prec, info->symbol); Reviewed-by: Radu Rendec