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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a7190ca9d6sm78325155ad.25.2026.01.19.00.48.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jan 2026 00:48:52 -0800 (PST) Message-ID: Date: Mon, 19 Jan 2026 16:48:49 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] wifi: ath12k: fix endianness handling for SRNG ring pointer accesses To: Alexander Wilhelm , Jeff Johnson Cc: ath12k@lists.infradead.org, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260119073923.764245-1-alexander.wilhelm@westermo.com> From: Baochen Qiang Content-Language: en-US In-Reply-To: <20260119073923.764245-1-alexander.wilhelm@westermo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE5MDA3MSBTYWx0ZWRfX6vO6sAcYJG3F NhLORG0mJH+/3f7DRV73m5FROQJoy55blYXlIIQ+AnNZzWjbKh8VEd87kHPU65eHXCPDyctsB2a ZKJOkO0He6ND/W5I7WG6jU8FGUoL3UBJu2hzPjGQ00x1Sayrl67JtNhEbymSYpZ1bFsq+F80vqW cfbwqBwiYc3i+j+/N6brpFKkx+khu42CEnWKX7N3ckdpipTlB8T6UqOPZWDl/+fCF5/bAQ1y4Vr RRINNQQhpiettI9Cj8DKRNnUlfZ7Ztn76lCMpj+Ks+LwcfDjPCer0Usd4yYeMMzW27uABQdyt1a na7cEJnvAgsXvGPpFyd6BKSkraBqOPshiW+c9XByviu4Bj1eZhYqMDd1GDelKYvC18gn3wiPbu6 O0EEKwkySOQ9UhaTsctWGBl7a0zAmrfjOY5bcGwLAmX1b3cZ8SogH3vmi9BBcebm6LiqbkL9sHX cPjrYSfjf7kKIitWE+A== X-Authority-Analysis: v=2.4 cv=NY3rFmD4 c=1 sm=1 tr=0 ts=696deff5 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=N9GNhs4bAAAA:8 a=EUspDBNiAAAA:8 a=dxIy8T9YzDl2N4HinIcA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=PZhj9NlD-CKO8hVp7yCs:22 X-Proofpoint-ORIG-GUID: aM2HDBwz1ZiXpDrhRKxtHbeCFtEf2eyo X-Proofpoint-GUID: aM2HDBwz1ZiXpDrhRKxtHbeCFtEf2eyo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-19_01,2026-01-19_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601190071 On 1/19/2026 3:39 PM, Alexander Wilhelm wrote: > The SRNG head and tail ring pointers are stored in device memory as > little-endian values. On big-endian systems, direct dereferencing of these > pointers leads to incorrect values being read or written, causing ring > management issues and potentially breaking data flow. > > This patch ensures all accesses to SRNG ring pointers use the appropriate > endianness conversions. This affects both read and write paths for source > and destination rings, as well as debug output. The changes guarantee > correct operation on both little- and big-endian architectures. > > Signed-off-by: Alexander Wilhelm > --- > Changes in v3: > - Rebase on latest 'ath' master > - Use always 'le32_to_cpu()' macro for conversions > > Changes in v2: > - Set '__le32 *' type for 'hp_addr/tp_addr' in both 'dst_ring' and 'src_ring' > --- > drivers/net/wireless/ath/ath12k/hal.c | 37 +++++++++++++++------------ > drivers/net/wireless/ath/ath12k/hal.h | 8 +++--- > 2 files changed, 25 insertions(+), 20 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c > index a164563fff28..28d0ff524fc6 100644 > --- a/drivers/net/wireless/ath/ath12k/hal.c > +++ b/drivers/net/wireless/ath/ath12k/hal.c > @@ -355,7 +355,7 @@ int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, > tp = srng->u.dst_ring.tp; > > if (sync_hw_ptr) { > - hp = *srng->u.dst_ring.hp_addr; > + hp = le32_to_cpu(*srng->u.dst_ring.hp_addr); > srng->u.dst_ring.cached_hp = hp; > } else { > hp = srng->u.dst_ring.cached_hp; > @@ -379,7 +379,7 @@ int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng, > hp = srng->u.src_ring.hp; > > if (sync_hw_ptr) { > - tp = *srng->u.src_ring.tp_addr; > + tp = le32_to_cpu(*srng->u.src_ring.tp_addr); > srng->u.src_ring.cached_tp = tp; > } else { > tp = srng->u.src_ring.cached_tp; > @@ -500,10 +500,10 @@ void ath12k_hal_srng_access_begin(struct ath12k_base *ab, struct hal_srng *srng) > lockdep_assert_held(&srng->lock); > > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > - srng->u.src_ring.cached_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + srng->u.src_ring.cached_tp = le32_to_cpu( > + *(volatile __le32 *)srng->u.src_ring.tp_addr); > } else { > - hp = READ_ONCE(*srng->u.dst_ring.hp_addr); > + hp = le32_to_cpu(READ_ONCE(*srng->u.dst_ring.hp_addr)); > > if (hp != srng->u.dst_ring.cached_hp) { > srng->u.dst_ring.cached_hp = hp; > @@ -528,25 +528,28 @@ void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng) > * hence written to a shared memory location that is read by FW > */ > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > - srng->u.src_ring.last_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + srng->u.src_ring.last_tp = le32_to_cpu( > + *(volatile __le32 *)srng->u.src_ring.tp_addr); > /* Make sure descriptor is written before updating the > * head pointer. > */ > dma_wmb(); > - WRITE_ONCE(*srng->u.src_ring.hp_addr, srng->u.src_ring.hp); > + WRITE_ONCE(*srng->u.src_ring.hp_addr, > + cpu_to_le32(srng->u.src_ring.hp)); > } else { > - srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; > + srng->u.dst_ring.last_hp = > + le32_to_cpu(*srng->u.dst_ring.hp_addr); > /* Make sure descriptor is read before updating the > * tail pointer. > */ > dma_mb(); > - WRITE_ONCE(*srng->u.dst_ring.tp_addr, srng->u.dst_ring.tp); > + WRITE_ONCE(*srng->u.dst_ring.tp_addr, > + cpu_to_le32(srng->u.dst_ring.tp)); > } > } else { > if (srng->ring_dir == HAL_SRNG_DIR_SRC) { > - srng->u.src_ring.last_tp = > - *(volatile u32 *)srng->u.src_ring.tp_addr; > + srng->u.src_ring.last_tp = le32_to_cpu( > + *(volatile __le32 *)srng->u.src_ring.tp_addr); > /* Assume implementation use an MMIO write accessor > * which has the required wmb() so that the descriptor > * is written before the updating the head pointer. > @@ -556,7 +559,8 @@ void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng) > (unsigned long)ab->mem, > srng->u.src_ring.hp); > } else { > - srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; > + srng->u.dst_ring.last_hp = > + le32_to_cpu(*srng->u.dst_ring.hp_addr); > /* Make sure descriptor is read before updating the > * tail pointer. > */ > @@ -711,7 +715,7 @@ void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, > * HP only when then ring isn't' empty. > */ > if (srng->ring_dir == HAL_SRNG_DIR_SRC && > - *srng->u.src_ring.tp_addr != srng->u.src_ring.hp) > + le32_to_cpu(*srng->u.src_ring.tp_addr) != srng->u.src_ring.hp) > ath12k_hal_srng_access_end(ab, srng); > } > > @@ -810,14 +814,15 @@ void ath12k_hal_dump_srng_stats(struct ath12k_base *ab) > "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %ums\n", > srng->ring_id, srng->u.src_ring.hp, > srng->u.src_ring.reap_hp, > - *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, > + le32_to_cpu(*srng->u.src_ring.tp_addr), > + srng->u.src_ring.cached_tp, > srng->u.src_ring.last_tp, > jiffies_to_msecs(jiffies - srng->timestamp)); > else if (srng->ring_dir == HAL_SRNG_DIR_DST) > ath12k_err(ab, > "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %ums\n", > srng->ring_id, srng->u.dst_ring.tp, > - *srng->u.dst_ring.hp_addr, > + le32_to_cpu(*srng->u.dst_ring.hp_addr), > srng->u.dst_ring.cached_hp, > srng->u.dst_ring.last_hp, > jiffies_to_msecs(jiffies - srng->timestamp)); > diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h > index 43e3880f8257..ff6148be94c8 100644 > --- a/drivers/net/wireless/ath/ath12k/hal.h > +++ b/drivers/net/wireless/ath/ath12k/hal.h > @@ -914,7 +914,7 @@ struct hal_srng { > u32 tp; > > /* Shadow head pointer location to be updated by HW */ > - volatile u32 *hp_addr; > + volatile __le32 *hp_addr; > > /* Cached head pointer */ > u32 cached_hp; > @@ -923,7 +923,7 @@ struct hal_srng { > * will be a register address and need not be > * accessed through SW structure > */ > - u32 *tp_addr; > + __le32 *tp_addr; > > /* Current SW loop cnt */ > u32 loop_cnt; > @@ -943,7 +943,7 @@ struct hal_srng { > u32 reap_hp; > > /* Shadow tail pointer location to be updated by HW */ > - u32 *tp_addr; > + __le32 *tp_addr; > > /* Cached tail pointer */ > u32 cached_tp; > @@ -952,7 +952,7 @@ struct hal_srng { > * will be a register address and need not be accessed > * through SW structure > */ > - u32 *hp_addr; > + __le32 *hp_addr; > > /* Low threshold - in number of ring entries */ > u32 low_threshold; > > base-commit: 758064145fe77e06d07661b27dfa9c24fe0309a3 Reviewed-by: Baochen Qiang