From: Dave Jiang <dave.jiang@intel.com>
To: Richard Cheng <icheng@nvidia.com>,
dave@stgolabs.net, jic23@kernel.org, alison.schofield@intel.com,
vishal.l.verma@intel.com
Cc: iweiny@kernel.org, ming.li@zohomail.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com,
kristinc@nvidia.com
Subject: Re: [PATCH] cxl/port: Fix endpoint RAS error unmasking
Date: Fri, 30 Oct 2026 10:08:13 -0700 [thread overview]
Message-ID: <b9539a2c-fbe3-4043-9347-b60cbc375fe1@intel.com> (raw)
In-Reply-To: <20261030095923.46051-1-icheng@nvidia.com>
On 10/30/26 2:59 AM, Richard Cheng wrote:
> Commit dab7162d0ae7 ("cxl/port: Move endpoint component register
> management to cxl_port") moved EP RAS handling from cxl_pci to cxl_port,
> while cxl_ras_unmask() have the assumption that port->uport_dev is a PCI
s/have/has/
> device.
> If the topology use cxl_memdev as uport_dev, the PCI check will fail and
> CXL RAS masks remain set.
Endpoint ports always use memdev as uport_dev right? Maybe we can say the unmask has never run.
>
> Resolve memdev uports to their parent dev and verify the device is PCI.
>
> Fixes: dab7162d0ae7 ("cxl/port: Move endpoint component register management to cxl_port")
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
> Reproducer is a QEMU Type-3 guest
>
> 1. Ensure no CXL region is active and PCIe AER is enabled.
> 2. Restore the emulated RAS registers to their reset masks.
> 3. Reprobe cxl_pci and read the masks again.
>
> ```
> BDF=$(basename "$(dirname "$(readlink -f /sys/bus/cxl/devices/mem0)")")
> BAR0=$(awk 'NR == 1 { print $1 }' /sys/bus/pci/devices/$BDF/resource)
> UNC_MASK=$(printf '0x%x' $((BAR0 + 0x1084)))
> COR_MASK=$(printf '0x%x' $((BAR0 + 0x1090)))
>
> busybox devmem "$UNC_MASK" 32 0x1cfff
> busybox devmem "$COR_MASK" 32 0x7f
>
> echo "$BDF" > /sys/bus/pci/drivers/cxl_pci/unbind
> echo "$BDF" > /sys/bus/pci/drivers/cxl_pci/bind
> udevadm settle
>
> busybox devmem "$UNC_MASK" 32
> busybox devmem "$COR_MASK" 32
> ```
>
> Before the fix, the masks remain 0x1cfff and 0x7f. After the fix,
> both masks read as zero.
>
> Best regards,
> Richard Cheng.
> ---
> drivers/cxl/port.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index c12fd0b89883..c48216e5078f 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -74,15 +74,18 @@ static int cxl_switch_port_probe(struct cxl_port *port)
>
> static int cxl_ras_unmask(struct cxl_port *port)
> {
> + struct device *host = port->uport_dev;
> struct pci_dev *pdev;
> void __iomem *addr;
> u32 orig_val, val, mask;
> u16 cap;
> int rc;
>
> - if (!dev_is_pci(port->uport_dev))
> + if (is_cxl_memdev(host))
> + host = host->parent;
> + if (!host || !dev_is_pci(host))
> return 0;
> - pdev = to_pci_dev(port->uport_dev);
> + pdev = to_pci_dev(host);
Can we simplify this to something like:
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
struct device *parent = cxlmd->dev.parent;
if (!dev_is_pci(parent))
return 0;
pdev = to_pci_dev(parent));
Also, maybe we should rename it to cxl_endpoint_ras_unmask(struct cxl_port *endpoint) to be intentionally clear?
>
> if (!port->regs.ras) {
> pci_dbg(pdev, "No RAS registers.\n");
>
> base-commit: d135ab453a7400a34930bdda1ef4bdc8acfac80e
prev parent reply other threads:[~2026-10-30 17:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 9:59 Richard Cheng
2026-10-30 17:08 ` Dave Jiang [this message]
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