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Tue, 28 May 2024 04:40:00 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 28 May 2024 04:39:59 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 28 May 2024 04:39:59 -0500 Received: from [10.24.68.216] (a0498981-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.216]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44S9dt3X041012; Tue, 28 May 2024 04:39:56 -0500 Message-ID: Date: Tue, 28 May 2024 15:09:55 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-j722s-evm: Enable main_uart5 Content-Language: en-US To: , CC: , , , , , , References: <20240528093911.47786-1-b-kapoor@ti.com> From: Bhavya Kapoor In-Reply-To: <20240528093911.47786-1-b-kapoor@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 28/05/24 3:09 pm, Bhavya Kapoor wrote: > main_uart5 node defined in the SoC dtsi file is incomplete > and will not be functional unless it is extended with pinmux > information at board integration level. > > Thus, add pinmux for main_uart5 in the board dts file and > enable it to make it functional. > > Signed-off-by: Bhavya Kapoor > --- rebased to next-20240528 > arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > index bf3c246d13d1..e3892a6f2fab 100644 > --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > @@ -18,6 +18,7 @@ / { > aliases { > serial0 = &wkup_uart0; > serial2 = &main_uart0; > + serial3 = &main_uart5; > mmc0 = &sdhci0; > mmc1 = &sdhci1; > }; > @@ -142,6 +143,14 @@ J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ > bootph-all; > }; > > + main_uart5_pins_default: main-uart5-default-pins { > + pinctrl-single,pins = < > + J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */ > + J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */ > + >; > + bootph-all; > + }; > + > vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { > pinctrl-single,pins = < > J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ > @@ -240,6 +249,13 @@ &main_uart0 { > bootph-all; > }; > > +&main_uart5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_uart5_pins_default>; > + status = "okay"; > + bootph-all; > +}; > + > &mcu_pmx0 { > > wkup_uart0_pins_default: wkup-uart0-default-pins {