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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF000044A1.mail.protection.outlook.com (10.167.243.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Wed, 3 Jun 2026 15:12:46 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 3 Jun 2026 10:12:35 -0500 Received: from localhost (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41 via Frontend Transport; Wed, 3 Jun 2026 10:12:35 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Conor Dooley , Krzysztof Kozlowski , "Michael Turquette" , Rob Herring , Shubhrajyoti Datta , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:COMMON CLK FRAMEWORK" Subject: [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Date: Wed, 3 Jun 2026 17:12:09 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UOICn/LFrpiJVTsrBiBIwC2n2RMATw7ebXqRScgahZQdZcBQzRWqlPDEfPY/OwXTFnV/e+2D6I38hte0tpRXnSpRcet+9Z8SjRc7IsnaWw9lUHLN0ifGF66ttxMFqZH1HviCql+uKu7jBK1XIBlqHDbGJkC7l3wbUZKzfuCqCXsDtyR8GQwXqn8o3EYnFNMwBnxXQNGGXxCM6aLxco1diJ97w1oU5Ox53qMe9HAGdjX4udoow63aLusk1W07pFNKNtfbHuSq6ZLpcpsqGLU2lQGKH1G3BMdLPNXGgmVGUW8M9yuMtR2B1G56gCy2ECN1Kh92akaVf3e6tnFliJk1N3Tett7MmzzaDmRJtRU+mEPEL9HXGuLVdiJiH0drd8o0lA2NmL0JYJKLd2yEwzkawn6mPEGp8ZfmJMSYAJAx95OrXhsPUd3Y+UJ8JcDlEfLb X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 15:12:46.8768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af29d3cb-bd86-4a19-ecd0-08dec18291cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6173 The Versal NET clock controller compatible is specified as: compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET. Define clock-names at the top-level and use if/then only to constrain the clock count (2 for Versal, 3 for Versal NET). Add a dedicated example for the Versal NET 3-clock configuration. Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal") Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Changes in v3: - Move clock-cells to be the last property in the example - use 2 spaces for indentation in example to follow the same style which is already used - Add fixed tag Changes in v2: - Update logic without ZynqMP part in this file and have if/else only around min/maxItems .../bindings/clock/xlnx,versal-clk.yaml | 51 ++++++++----------- 1 file changed, 22 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 12d060c39bfc..b533ffd082fd 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -30,11 +30,17 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 3 + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock clock-names: minItems: 2 - maxItems: 3 + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref required: - compatible @@ -50,40 +56,19 @@ allOf: compatible: contains: enum: - - xlnx,versal-clk - + - xlnx,versal-net-clk then: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - + minItems: 3 clock-names: - items: - - const: ref - - const: pl_alt_ref - - - if: - properties: - compatible: - contains: - enum: - - xlnx,versal-net-clk - - then: + minItems: 3 + else: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - description: alternate reference clock - + maxItems: 2 clock-names: - items: - - const: ref - - const: pl_alt_ref - - const: alt_ref + maxItems: 2 examples: - | @@ -99,4 +84,12 @@ examples: }; }; }; + + - | + clock-controller { + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; + }; ... -- 2.43.0