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([2a02:1807:2a00:3400:b63f:533e:fab7:5343]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c074879fe5sm10591690f8f.2.2025.08.21.01.12.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Aug 2025 01:12:12 -0700 (PDT) Message-ID: Date: Thu, 21 Aug 2025 10:12:11 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1 To: Yixun Lan Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org References: <20250807191817.157494-1-hendrik.hamerlinck@hammernet.be> <20250820231917-GYB1065530@gentoo> Content-Language: en-US From: Hendrik Hamerlinck In-Reply-To: <20250820231917-GYB1065530@gentoo> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hello Yixun, On 8/21/25 01:19, Yixun Lan wrote: > Hi Hendrik, > > On 21:18 Thu 07 Aug , Hendrik Hamerlinck wrote: >> Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree. >> UART0 was functional as it did not need a reset. But the other UARTs were >> unable to access their registers without the reset being applied. >> > .. >> Although perhaps not needed I did add the reset for UART0 as well, >> to ensure consistency across all UARTs. With the current-speed set to >> 112500 baud rate, it matches the factory U-Boot settings. >> This should not give issues with early console usage. But perhaps it could >> be a good idea to let somebody else confirm this as well. >> > Adding reset to UART0 is just fine, so we don't need to presume it will > rely on bootloader to de-assert the controller > > please write changelogs in imperative mood, you can follow > https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog Ok, I’ll update the changelog accordingly in v2. > >> Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. >> I enabled the UART9 and was able to use it successfully. >> >> Signed-off-by: Hendrik Hamerlinck >> --- >> arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi >> index abde8bb07c95..7a5196a98085 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi >> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi >> @@ -667,6 +667,8 @@ uart0: serial@d4017000 { >> clocks = <&syscon_apbc CLK_UART0>, >> <&syscon_apbc CLK_UART0_BUS>; >> clock-names = "core", "bus"; > .. >> + current-speed = <115200>; > please drop this property, dtsi file should contain generic info for SoC, > even in real cases, all boards use UART0 as serial output and configured > at baudrate 115200, it still be able to alter to different frequency.. > > besides, if you really want to set baudrate, then I'd suggest to configure > it at board specific dts file, > stdout-path = "serial0:115200n8"; Understood, I’ll drop the `current-speed` property. It works without it. Thanks for the review. Kind regards, Hendrik