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Wed, 21 Oct 2026 08:53:49 -0700 (PDT) Received: from [192.168.1.10] ([122.164.81.208]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1903a275026sm11144550c88.5.2026.10.21.08.53.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 08:53:48 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 21:23:41 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] clk: qcom: clk-alpha-pll: Skip Zonda PLL configuration if already enabled To: Konrad Dybcio , Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> <20261007-ipq9650_apss_clk-v1-2-fd4c2b3cbdea@oss.qualcomm.com> <3faeade1-1bd2-4e74-95ae-7396a1ef1ce4@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <3faeade1-1bd2-4e74-95ae-7396a1ef1ce4@oss.qualcomm.com> Content-Type: text/plain; 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When >> the APSS clock driver probes, it attempts to reconfigure the already >> running PLLs. As part of the reconfiguration sequence, the PLL output is >> disabled and the PLL is placed into standby before being re-enabled. >> Since the CPUs are actively clocked from these PLLs, removing the clock >> during this window causes the system to hang. >> >> Avoid reconfiguring PLLs that are already enabled and return early, >> similar to clk_trion_pll_configure(). >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- >> drivers/clk/qcom/clk-alpha-pll.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c >> index 60173b076cc5..3641b2da92cd 100644 >> --- a/drivers/clk/qcom/clk-alpha-pll.c >> +++ b/drivers/clk/qcom/clk-alpha-pll.c >> @@ -2162,6 +2162,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); >> void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >> const struct alpha_pll_config *config) >> { >> + /* Check if PLL is already enabled */ >> + if (trion_pll_is_enabled(pll, regmap)) >> + return; > Please add a debug print to match the other similar calls Ack. I see in some places, debug prints are not available. Let me add that as a separate patch to make it consistent throughout the driver. > > with that: > > Reviewed-by: Konrad Dybcio > > Konrad