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Sun, 07 Jun 2026 22:39:30 -0700 (PDT) X-Received: by 2002:a17:90b:548e:b0:369:e4d4:79c6 with SMTP id 98e67ed59e1d1-370f0b55fbemr14256589a91.20.1780897170005; Sun, 07 Jun 2026 22:39:30 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3712ef0add7sm8612386a91.0.2026.06.07.22.39.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 Jun 2026 22:39:29 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 11:09:22 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH v7 07/12] media: iris: Add power sequence for glymur To: Dmitry Baryshkov Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20260603-glymur-v7-0-afaa55d11fe0@oss.qualcomm.com> <20260603-glymur-v7-7-afaa55d11fe0@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDA0OSBTYWx0ZWRfXz6ydK5pXMajA qv9uUin4fZDl2ugR6AJ/mSlmF/Zpq76TJkokcXv2xYnC/NlW00esfOqxOHNE4EmAETiZs6mG2Ay xDxflUNohicV7YBLNi6Ai44Nx8t6Zarf/tK2AKwkL3oGDCLmLUB/Fj3uYLTtOD/eVv1eg/yuFph JsPl2mYaeT9+obUPRSgGjgSc+Lt6yBmHGuUYOABmPs9fu8ixpFvAiEXixM1jKNOoUheqI5gYAJL UszTFLYXSDXFuJjQbxQM/seSn9qkVXcj3za+FYN2U+dMX7MwypKYUhxzu55tGUVf57Mk/w2CL9I iYMHo/EzHY8/5CEQ1efKKbUuDAr3QC/djvxEgGCXCCsK86IcXoL8t7MMiLGXcZWd3cA3ZsUZvam E5DloqL0KWRbxPfcfaDX6bB/14wAv71g73BnEZzvO9WQdH92XuWkBGlaWgatL+a30a2YbKXaY4C wV6+ls9XcyU1Qq4trhw== X-Proofpoint-ORIG-GUID: MuzQIr28QG1d9HtJKrtXGP07q97JK8ye X-Proofpoint-GUID: MuzQIr28QG1d9HtJKrtXGP07q97JK8ye X-Authority-Analysis: v=2.4 cv=A/pc+aWG c=1 sm=1 tr=0 ts=6a265593 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=XOSsvO-zd5c9LZtoon0A:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_01,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080049 On 6/8/2026 3:17 AM, Dmitry Baryshkov wrote: > On Wed, Jun 03, 2026 at 07:48:45PM +0530, Vishnu Reddy wrote: >> Glymur platform has two video codec cores: vcodec0 and vcodec1. >> >> Both cores share a common clock source (video_cc_mvs0_clk_src) and the >> same power rails. The clock dividers between the source and the branch >> clocks are fixed. So when both cores are running, the source clock always >> runs at the highest frequency requested by either core. >> >> Since both cores share the same power rails, the power corner cannot be >> voted independently. Scaling one core's power corner up or down would >> directly affect the other, leading to under or over-voting. >> >> For these reasons, both cores should voted the clock and power rail must >> be based on the workload of both cores. >> >> Reviewed-by: Vikash Garodia >> Signed-off-by: Vishnu Reddy >> --- >> drivers/media/platform/qcom/iris/iris_vpu3x.c | 111 ++++++++++++++++++++- >> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + >> .../platform/qcom/iris/iris_vpu_register_defines.h | 10 ++ >> 3 files changed, 117 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c >> index 7cda94601555..f07eaf4b3be2 100644 >> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c >> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c >> @@ -17,14 +17,14 @@ >> #define NOC_HALT BIT(0) >> #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) >> >> -static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) >> +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core, u32 pwr_status_bit) >> { >> u32 value, pwr_status; >> >> value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >> - pwr_status = value & BIT(1); >> + pwr_status = value & pwr_status_bit; >> >> - return pwr_status ? false : true; >> + return !pwr_status; >> } >> >> static void iris_vpu3_power_off_hardware(struct iris_core *core) >> @@ -32,7 +32,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) >> u32 reg_val = 0, value, i; >> int ret; >> >> - if (iris_vpu3x_hw_power_collapsed(core)) >> + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) >> goto disable_power; >> >> dev_err(core->dev, "video hw is power on\n"); >> @@ -78,7 +78,7 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) >> u32 count = 0; >> int ret; >> >> - if (iris_vpu3x_hw_power_collapsed(core)) >> + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) >> goto disable_power; >> >> dev_err(core->dev, "video hw is power on\n"); >> @@ -221,6 +221,98 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) >> iris_vpu33_power_off_hardware(core); >> } >> >> +static void iris_vpu36_power_off_vcodec(struct iris_core *core, u32 core_id) >> +{ >> + u32 value, i; >> + int ret; >> + >> + if (iris_vpu3x_hw_power_collapsed(core, >> + core_id ? VCODEC1_POWER_STATUS : VCODEC0_POWER_STATUS)) >> + goto disable_power; >> + >> + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + if (value) >> + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + >> + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { >> + ret = readl_poll_timeout(core->reg_base + (core_id ? VCODEC1_SS_IDLE_STATUSN : >> + VCODEC_SS_IDLE_STATUSN) + 4 * i, value, >> + value & DMA_NOC_IDLE, 2000, 20000); > Unreadable. Extract register addresses to separate variables. Ack >> + if (ret) >> + goto disable_power; >> + } >> + >> + writel(core_id ? REQ_VCODEC1_POWER_DOWN_PREP : REQ_POWER_DOWN_PREP, >> + core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, value, >> + value & (core_id ? NOC_LPI_VCODEC1_STATUS_DONE : >> + NOC_LPI_STATUS_DONE), 2000, 20000); >> + if (ret) >> + goto disable_power; >> + >> + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); >> + >> + writel((core_id ? VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE : >> + CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE), >> + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >> + writel(core_id ? VCODEC1_BRIDGE_HW_RESET_DISABLE : CORE_BRIDGE_HW_RESET_DISABLE, >> + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >> + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >> + >> +disable_power: >> + dev_pm_genpd_set_hwmode(core->vcodec[core_id].dev, false); >> + iris_disable_power_domain_and_clocks(core, &core->vcodec[core_id]); >> +} >> + >> +static void iris_vpu36_power_off_hw(struct iris_core *core) >> +{ >> + u32 num_cores = max(core->iris_platform_data->num_cores, 1); > Can we trust the patch authors that VPU3.6 hardware data will have at > least 1 core? On Glymur (VPU3.6), num_cores is 2. The max() guard is unnecessary. Will access num_cores directly. >> + int i; >> + >> + for (i = 0; i < num_cores; i++) >> + iris_vpu36_power_off_vcodec(core, i); >> +} >> + >> #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) >> #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > Lowercase hex. Ack >> #define REQ_POWER_DOWN_PREP BIT(0) >> +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) >>