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([2001:b07:6468:f312:9af8:e5f5:7516:fa89]) by smtp.googlemail.com with ESMTPSA id f17-20020a056402161100b00537666d307csm1351182edv.32.2023.10.05.10.14.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Oct 2023 10:14:44 -0700 (PDT) Message-ID: Date: Thu, 5 Oct 2023 19:14:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] x86: KVM: Add feature flag for AMD's FsGsKernelGsBaseNonSerializing Content-Language: en-US To: Jim Mattson Cc: Borislav Petkov , Dave Hansen , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Pawan Gupta , Jiaxi Chen , Kim Phillips , Sean Christopherson , "H. Peter Anvin" , x86@kernel.org, Dave Hansen , Ingo Molnar , Thomas Gleixner References: <20231004002038.907778-1-jmattson@google.com> <01009a2a-929e-ce16-6f44-1d314e6bcba5@intel.com> <20231004075836.GBZR0bLC/Y09sSSYWw@fat_crate.local> <8c810f89-43f3-3742-60b8-1ba622321be8@redhat.com> From: Paolo Bonzini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/5/23 19:06, Jim Mattson wrote: > On Thu, Oct 5, 2023 at 9:39 AM Paolo Bonzini wrote: > >> I agree with Jim that it would be nice to have some bits from Intel, and >> some bits from AMD, that current processors always return as 1. Future >> processors can change those to 0 as desired. > That's not quite what I meant. > > I'm suggesting a leaf devoted to single bit negative features. If a > bit is set in hardware, it means that something has been taken away. > Hypervisors don't need to know exactly what was taken away. For this > leaf only, hypervisors will always pass through a non-zero bit, even > if they have know idea what it means. Understood, but I'm suggesting that these might even have the right polarity: if a bit is set it means that something is there and might not in the future, even if we don't know exactly what. We can pass through the bit, we can AND bits across the migration pool to define what to pass to the guest, we can force-set the leaves to zero (feature removed). Either way, the point is to group future defeatures together. That said, these bits are only for documentation/debugging purposes anyway. So I like the idea because it would educate the architects about this issue, more than because it is actually useful... Paolo