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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="=-XM3erh92RLIAuvrENta7" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV2PR02MB8434.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5aaa5744-70a2-4c2b-109a-08df22f1bb54 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Oct 2026 15:02:53.4605 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bsoScU6bfOjnu5T/UmOejJ/pcRDfT4FAFzjbA/8ltBRrFPXTllMJew5sojcmTgu4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR02MB6021 --=-XM3erh92RLIAuvrENta7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Andy, On Sat, 2026-10-03 at 18:02 +0300, andriy.shevchenko@intel.com wrote: > On Fri, Oct 02, 2026 at 02:25:48PM +0000, Kanak Shilledar wrote: >=20 > > On Fri, 2026-10-02 at 16:12 +0300, Andy Shevchenko wrote: > > > On Fri, Oct 02, 2026 at 01:54:29PM +0200, Kanak Shilledar wrote: >=20 > ... >=20 > > > > +static int inv_icm42607_mreg_read(struct regmap *map, unsigned > > > > int > > > > reg, > > > > + =C2=A0 u8 *data, size_t count) > > > > +{ > > > > + unsigned int val; > > > > + bool idle_set; > > > >=20 ... > > > > + > > > > + return ret; > > > > =C2=A0} >=20 > ... >=20 > > > > +static const struct regmap_config inv_icm42607_regmap_config =3D > > > > { > > > > + .reg_bits =3D 8, > > > > + .val_bits =3D 8, > > >=20 > > > No cache? Why? > > As the virtual regmap config has some caching for USER BANK 0 > > registers > > only. The indirect banks doesn't support caching [1]. >=20 > This is strange. You mean they are volatile by definition (HW)? > Otherwise if it's just a software issue, it can still be done, > for regcache there is no difference if the offset is real or paged. Sorry, I was not very clear in the explanation about caches. Only some specific MREGx registers are volatile and I am not using those yet. I have removed the MREGx registers from the _is_volatile_reg function. In this 8-bit transport regmap I am not using any caching because the 16-bit virtual regmap (in _core.c) already knows all the registers (readable/writeable/volatile) and also contains a cache. Everything which reaches the transport regmap is either a write or read which was missed in the virtual cache or an access to the bank switching registers which should always reach the hardware. I tried adding REGCACHE_MAPLE in the transport regmap, but accessing registers in MREG1 then timed out due to stale cached values. > > >=20 > > [1] Datasheet: https://www.lcsc.com/product-detail/C5129967.html Thanks and Regards, Kanak Shilledar --=-XM3erh92RLIAuvrENta7 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTOMrdbv2P+LZwbQtLEY9j7t8KaZwUCasO8GwAKCRDEY9j7t8Ka Z6bUAP9KosDIvgBW+cAT+z3UnmLdTLaZKTr0o/rLuuQwDny33gEAyaHuOVXpXK6/ Qa6t907KPTcePARzH35XeRk4/eHTdwI= =q/2n -----END PGP SIGNATURE----- --=-XM3erh92RLIAuvrENta7--