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Fri, 08 Aug 2025 10:22:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFi0ezLAvd5RkULpFWK7WLTaadsd+/Ps2gsqlHJKq3156s96y5T3Pq4HOvg12o43Wrff+vHAA== X-Received: by 2002:a05:6a20:7d9f:b0:240:1132:6f0 with SMTP id adf61e73a8af0-240551eeac0mr6475822637.43.1754673745264; Fri, 08 Aug 2025 10:22:25 -0700 (PDT) Received: from [192.168.1.4] ([106.222.234.151]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b422bac0d14sm18058211a12.41.2025.08.08.10.22.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 10:22:24 -0700 (PDT) Message-ID: Date: Fri, 8 Aug 2025 22:52:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/17] drm/msm/a6xx: Fix PDC sleep sequence To: Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-5-9347aa5bcbd6@oss.qualcomm.com> <937197e9-09dd-4f3c-bdb4-4001f5217c07@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <937197e9-09dd-4f3c-bdb4-4001f5217c07@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Q+XS452a c=1 sm=1 tr=0 ts=68963252 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=YZlS21pjlsXJIaRBoB+Oqw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=g_v6zqOf2VaQD3ULXM8A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: Dkv68EAeFkimVdSPM4ZVu9iQONRaQ2bz X-Proofpoint-ORIG-GUID: Dkv68EAeFkimVdSPM4ZVu9iQONRaQ2bz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA3MDA2OSBTYWx0ZWRfX6BA6mb9JKjld MULjoilqy7M+h12Ld2O7qGm5p365hrUPbY8z5hzzf9v9EnApWfipQUGfV+sX1O41XtZb+GRAuqV PARJhDRafyO4bj7eA8ucnerAiNRUgnHR/QUjzt0+Ftw/Om5xKEBrz+YvIoamQbd+gLnPfOhHUe1 u5v73dJn+gmrmQNfA8nlwKNxUJq29CU2WVxFGzhz6bFLOzfFRZ+Kjy0379WsV8+pR36/YGJ3Hr1 jjLLlSojjdqgMb0/oEc5G1UVhJAAggwlABy+dOIXyMtJibRZWiMaT/zoKT0IZuOzjV7PHUBU02U gRnmJRwsk0sAbhGbk/TtsYs5RlmU1CMnLPNunZJnyn/68sK9u4Ey+FInTWEfrID3ArcCPEhFmZY FBwWQIR9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_05,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508070069 On 8/7/2025 7:21 PM, Konrad Dybcio wrote: > On 7/20/25 2:16 PM, Akhil P Oommen wrote: >> Since the PDC resides out of the GPU subsystem and cannot be reset in >> case it enters bad state, utmost care must be taken to trigger the PDC >> wake/sleep routines in the correct order. >> >> The PDC wake sequence can be exercised only after a PDC sleep sequence. >> Additionally, GMU firmware should initialize a few registers before the >> KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the >> GMU firmware has not initialized. Track these dependencies using a new >> status variable and trigger PDC sleep/wake sequences appropriately. >> >> Signed-off-by: Akhil P Oommen >> --- > > FWIW some time ago I made this patch, which tackles a similar issue, > perhaps it's a good idea to merge both: > > From 7d6441fc6ec5ee7fe723e1ad86d11fdd17bee922 Mon Sep 17 00:00:00 2001 > From: Konrad Dybcio > Date: Thu, 20 Feb 2025 10:28:51 +0100 > Subject: [PATCH] drm/msm/adreno: Delay the Adreno RPMh startup to HFI init > > There's no use in trying to power up the GX logic before we're almost > ready to fire up the GPU. In fact, with A8xx the PDC and RSC uCode are > loaded by the GMU firmware, so we *must* wait for the GMU to fully > initialize before trying to do so. > iirc, this wake up sequence should be done before fw start. That aligns with downstream sequence order too. -Akhil > Move it to right before HFI init. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 12 ++---------- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 2 +- > 3 files changed, 4 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 28e6705c6da6..3335583ada45 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -513,7 +513,7 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) > return ret; > } > > -static int a6xx_rpmh_start(struct a6xx_gmu *gmu) > +int a6xx_rpmh_start(struct a6xx_gmu *gmu) > { > int ret; > u32 val; > @@ -842,19 +842,11 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > else > gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); > > - if (state == GMU_WARM_BOOT) { > - ret = a6xx_rpmh_start(gmu); > - if (ret) > - return ret; > - } else { > + if (state == GMU_COLD_BOOT) { > if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], > "GMU firmware is not loaded\n")) > return -ENOENT; > > - ret = a6xx_rpmh_start(gmu); > - if (ret) > - return ret; > - > ret = a6xx_gmu_fw_load(gmu); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index d1ce11131ba6..309305298a45 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -216,5 +216,6 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); > bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); > void a6xx_sptprac_disable(struct a6xx_gmu *gmu); > int a6xx_sptprac_enable(struct a6xx_gmu *gmu); > +int a6xx_rpmh_start(struct a6xx_gmu *gmu); > > #endif > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index 8e69b1e84657..9ea01daf2995 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -910,7 +910,7 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) > if (ret) > return ret; > > - return 0; > + return a6xx_rpmh_start(gmu); > } > > void a6xx_hfi_stop(struct a6xx_gmu *gmu)