Re: [PATCH v2 2/2] arm64: dts: qcom: ipq5018: Enable MDIO buses and add ethernet PHY

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 8/14/26 4:22 PM, Luo Jie wrote:
> Both the internal (mdio0) and external (mdio1) MDIO buses are present
> in the SoC dtsi but left disabled at the board level, so the board
> currently has no way to talk to PHYs on either bus.
> 
> The RDP432-c2 board uses the SoC-integrated EPHY on mdio0 and an
> external QCA8081 PHY on mdio1 for its Ethernet connections. Enable
> mdio0 and mdio1 with a 6.25MHz MDIO clock, and describe the QCA8081
> PHY at address 0x1c on mdio1.
> 
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> index 33eef92b19b1..aed8359b1931 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> @@ -30,6 +30,20 @@ &blsp1_uart1 {
>  	status = "okay";
>  };
>  
> +&mdio0 {
> +	clock-frequency = <6250000>;
> +	status = "okay";

If the phy is integrated as part of the SoC, is there a reason to
not enable this bus by default for all boards?

> +};
> +
> +&mdio1 {
> +	clock-frequency = <6250000>;
> +	status = "okay";

Nit: a newline before status would be neat

> +
> +	ethernet-phy@1c {

No compatible string and other properties?

Konrad