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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3ef86e514sm749680066b.35.2025.03.24.16.59.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 16:59:51 -0700 (PDT) Message-ID: Date: Tue, 25 Mar 2025 00:59:49 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC To: Konrad Dybcio , Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com References: <20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com> <20250321-qcom_ipq5424_cmnpll-v1-1-3ea8e5262da4@quicinc.com> <55eada15-222e-4b97-a519-95b5e3aa7c23@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <55eada15-222e-4b97-a519-95b5e3aa7c23@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: uAJLbDgc0h59T3oP9xftyb0JW4iCRN10 X-Proofpoint-ORIG-GUID: uAJLbDgc0h59T3oP9xftyb0JW4iCRN10 X-Authority-Analysis: v=2.4 cv=JvPxrN4C c=1 sm=1 tr=0 ts=67e1f1fb cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=BPsefSz62mVIWsVq_7wA:9 a=QEXdDO2ut3YA:10 a=RVmHIydaz68A:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-24_07,2025-03-21_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503240164 On 3/25/25 12:57 AM, Konrad Dybcio wrote: > On 3/21/25 1:49 PM, Luo Jie wrote: >> The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference >> input clock. The output clocks are the same as IPQ9574 SoC, except >> for the clock rate of output clocks to PPE and NSS. >> >> Also, add macros for clock rates that are applicable specifically >> only for IPQ5424. >> >> Signed-off-by: Luo Jie >> --- >> .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + >> include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 10 +++++++++- >> 2 files changed, 10 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >> index f869b3739be8..bbaf896ae908 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >> @@ -25,6 +25,7 @@ properties: >> compatible: >> enum: >> - qcom,ipq9574-cmn-pll >> + - qcom,ipq5424-cmn-pll >> >> reg: >> maxItems: 1 >> diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h >> index 936e92b3b62c..e30d57001c38 100644 >> --- a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h >> +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h >> @@ -1,6 +1,6 @@ >> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> /* >> - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H >> @@ -19,4 +19,12 @@ >> #define ETH1_50MHZ_CLK 7 >> #define ETH2_50MHZ_CLK 8 >> #define ETH_25MHZ_CLK 9 >> + >> +/* >> + * The CMN PLL output clock rates that are specifically applicable for IPQ5424 >> + * SoC. For IPQ5424, the other output clocks and their rates are same as IPQ9574. >> + */ >> +#define NSS_300MHZ_CLK 4 >> +#define PPE_375MHZ_CLK 5 > > Not a huge fan of this, such differences are only relevant to the driver > part in my view - bindings only let a consumer reference a specific piece > of hardware Oh I the bindings are stepping into the frequency department already, hmm.. Then I suppose it's fine if the dt-bindings maintainers don't have any concerns Konrad