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keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20240814-nwl-dsi-sync-polarity-v1-1-ee198e369196@geanix.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/08/2024 12:37, Esben Haabendal wrote: > Using the correct bit helps. The documentation specifies bit 0 in both > registers to be controlling polarity of dpi_vsync_input and > dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be > set. > > Tested with panel that requires active high vsync and hsync. > > Signed-off-by: Esben Haabendal > --- > drivers/gpu/drm/bridge/nwl-dsi.c | 8 ++++---- > drivers/gpu/drm/bridge/nwl-dsi.h | 4 ++-- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c > index 8d54091ec66e..5f05647a3bea 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -289,13 +289,13 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) > > nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); > nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); > - /* > - * Adjusting input polarity based on the video mode results in > - * a black screen so always pick active low: > - */ > nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, > + dsi->mode.flags & DRM_MODE_FLAG_PVSYNC ? > + NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH : > NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW); > nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, > + dsi->mode.flags & DRM_MODE_FLAG_PHSYNC ? > + NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH : > NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW); > > burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.h b/drivers/gpu/drm/bridge/nwl-dsi.h > index a247a8a11c7c..61e7d65cb1eb 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.h > +++ b/drivers/gpu/drm/bridge/nwl-dsi.h > @@ -30,11 +30,11 @@ > #define NWL_DSI_PIXEL_FORMAT 0x20c > #define NWL_DSI_VSYNC_POLARITY 0x210 > #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0 > -#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1) > +#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(0) > > #define NWL_DSI_HSYNC_POLARITY 0x214 > #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0 > -#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1) > +#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(0) > > #define NWL_DSI_VIDEO_MODE 0x218 > #define NWL_DSI_HFP 0x21c > > --- > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > change-id: 20240814-nwl-dsi-sync-polarity-ddc58435a4c4 > > Best regards, Reviewed-by: Neil Armstrong