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bh=eOZEdnbp46Z76LsK49tdtTNIOhWoViPgM8WCccLIHUE=; b=jnHZYsjvx4bgXFj2fwDjKLViSY7aFM9q4NORoOs0BAUUhH/SRf432yZgbOHMaP/PWKFYrOKUhOqShxi+hn8sMixSYSQ5r232ekx4Orp0a7vhLE8ba6JnaFAmyXM4VP48oRJY/JdmRYwaBbXUp3EWi/K9jqTUw5YT7cYLBEcRR4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=louisalexis.eyraud@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1771936826; s=zohomail; d=collabora.com; i=louisalexis.eyraud@collabora.com; h=Message-ID:Subject:Subject:From:From:To:To:Cc:Cc:Date:Date:In-Reply-To:References:Content-Type:Content-Transfer-Encoding:MIME-Version:Message-Id:Reply-To; bh=eOZEdnbp46Z76LsK49tdtTNIOhWoViPgM8WCccLIHUE=; b=MV5O3D43ndbEy9mp7nq8rtLMNyNdMG8MnNEj8pZPqcPhftte69WLFJV/+8o398ir hnrOTRXSzormLfL1sqLDROsM6DuSbgYyrUldvmoXs9AKEKiYHyLHp7IgeqoP0ObRD+6 16nALCxSkfRZeVakaq7j3J69dFlLJpiwcMVvkiJM= Received: by mx.zohomail.com with SMTPS id 1771936824130242.17321167502485; Tue, 24 Feb 2026 04:40:24 -0800 (PST) Message-ID: Subject: Re: [PATCH v5 06/18] clk: mediatek: Add MT8189 vlpcfg clock support From: Louis-Alexis Eyraud To: "irving.ch.lin" , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Qiqi Wang , sirius.wang@mediatek.com, vince-wl.liu@mediatek.com, jh.hsu@mediatek.com Date: Tue, 24 Feb 2026 13:40:16 +0100 In-Reply-To: <20260202062840.342707-7-irving-ch.lin@mediatek.com> References: <20260202062840.342707-1-irving-ch.lin@mediatek.com> <20260202062840.342707-7-irving-ch.lin@mediatek.com> Organization: Collabora Ltd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External Hi Irving-CH, On Mon, 2026-02-02 at 14:28 +0800, irving.ch.lin wrote: > From: Irving-CH Lin >=20 > Add support for the MT8189 vlpcfg clock controller, > which provides clock gate control for vlp domain IPs. >=20 > Signed-off-by: Irving-CH Lin > --- > =C2=A0drivers/clk/mediatek/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +- > =C2=A0drivers/clk/mediatek/clk-mt8189-vlpcfg.c | 111 > +++++++++++++++++++++++ > =C2=A02 files changed, 112 insertions(+), 1 deletion(-) > =C2=A0create mode 100644 drivers/clk/mediatek/clk-mt8189-vlpcfg.c >=20 > diff --git a/drivers/clk/mediatek/Makefile > b/drivers/clk/mediatek/Makefile > index 3b25df9e7b50..d9279b237b7b 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -124,7 +124,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk- > mt8188-venc.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk- > mt8188-vpp1.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk- > mt8189-topckgen.o \ > - =C2=A0=C2=A0 clk-mt8189-vlpckgen.o > + =C2=A0=C2=A0 clk-mt8189-vlpckgen.o clk-mt8189- > vlpcfg.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk- > mt8192.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o > =C2=A0obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o > diff --git a/drivers/clk/mediatek/clk-mt8189-vlpcfg.c > b/drivers/clk/mediatek/clk-mt8189-vlpcfg.c > new file mode 100644 > index 000000000000..2b9c3101f2b4 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt8189-vlpcfg.c > @@ -0,0 +1,111 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2025 MediaTek Inc. > + * Author: Qiqi Wang > + */ > + > +#include > +#include > +#include > +#include > + > +#include "clk-mtk.h" > +#include "clk-gate.h" > + > +#include > + > +static const struct mtk_gate_regs vlpcfg_ao_reg_cg_regs =3D { > + .set_ofs =3D 0x0, > + .clr_ofs =3D 0x0, > + .sta_ofs =3D 0x0, > +}; > + > +#define GATE_VLPCFG_AO_REG(_id, _name, _parent, > _shift) \ > + GATE_MTK(_id, _name, _parent, &vlpcfg_ao_reg_cg_regs, > _shift, &mtk_clk_gate_ops_no_setclr) > + > +static const struct mtk_gate vlpcfg_ao_reg_clks[] =3D { > + GATE_VLPCFG_AO_REG(CLK_VLPCFG_AO_APEINT_RX, > "vlpcfg_ao_apeint_rx", "clk26m", 8), > +}; > + > +static const struct mtk_clk_desc vlpcfg_ao_reg_mcd =3D { > + .clks =3D vlpcfg_ao_reg_clks, > + .num_clks =3D ARRAY_SIZE(vlpcfg_ao_reg_clks), > +}; > + > +static const struct mtk_gate_regs vlpcfg_reg_cg_regs =3D { > + .set_ofs =3D 0x4, > + .clr_ofs =3D 0x4, > + .sta_ofs =3D 0x4, > +}; > + > +#define GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, > _flags) \ > + GATE_MTK_FLAGS(_id, _name, _parent, &vlpcfg_reg_cg_regs, > _shift, \ > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 &mtk_clk_gate_ops_no_setclr_inv, = _flags) > + > +#define GATE_VLPCFG_REG(_id, _name, _parent, _shift) \ > + GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, 0) > + > +static const struct mtk_gate vlpcfg_reg_clks[] =3D { > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SCP, "vlpcfg_scp", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_scp_sel", 28, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_R_APXGPT_26M, > "vlpcfg_r_apxgpt_26m", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk26m", 24, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRCK_TEST, > "vlpcfg_dpmsrck_test", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk26m", 23, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, > "vlpcfg_dpmsrrtc_test", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk32k", 22, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRULP_TEST, > "vlpcfg_dpmsrulp_test", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "osc_d10", 21, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST, > "vlpcfg_spmi_p", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_spmi_p_sel", 20, > CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST_32K, > "vlpcfg_spmi_p_32k", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk32k", 18, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, > "vlpcfg_pmif_spmi_p_sys", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_pwrap_ulposc_sel", 13, > CLK_IS_CRITICAL), There is no such "vlp_pwrap_ulposc_sel" clock defined in your mt8189 clock driver patch series. The parent clock should probably be "vlp_pwrap_osc_sel" (that is defined in clk-mt8189-vlpckgen.c) instead. Same thing for vlpcfg_pmif_spmi_p_tmr, vlpcfg_pmif_spmi_m_sys and vlpcfg_pmif_spmi_m_tmr below that have the same parent clock. Best regards, Louis-Alexis > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, > "vlpcfg_pmif_spmi_p_tmr", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_pwrap_ulposc_sel", 12, > CLK_IS_CRITICAL), > + GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, > "vlpcfg_pmif_spmi_m_sys", > + "vlp_pwrap_ulposc_sel", 11), > + GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, > "vlpcfg_pmif_spmi_m_tmr", > + "vlp_pwrap_ulposc_sel", 10), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DVFSRC, > "vlpcfg_dvfsrc", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_dvfsrc_sel", 9, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PWM_VLP, > "vlpcfg_pwm_vlp", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_pwm_vlp_sel", 8, > CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SRCK, "vlpcfg_srck", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_srck_sel", 7, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F26M, > "vlpcfg_sspm_f26m", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_sspm_f26m_sel", 4, > CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F32K, > "vlpcfg_sspm_f32k", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk32k", 3, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_ULPOSC, > "vlpcfg_sspm_ulposc", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "vlp_sspm_ulposc_sel", 2, > CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_32K_COM, > "vlpcfg_vlp_32k_com", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk32k", 1, CLK_IS_CRITICAL), > + GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_26M_COM, > "vlpcfg_vlp_26m_com", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "clk26m", 0, CLK_IS_CRITICAL), > +}; > + > +static const struct mtk_clk_desc vlpcfg_reg_mcd =3D { > + .clks =3D vlpcfg_reg_clks, > + .num_clks =3D ARRAY_SIZE(vlpcfg_reg_clks), > +}; > + > +static const struct of_device_id of_match_clk_mt8189_vlpcfg[] =3D { > + { .compatible =3D "mediatek,mt8189-vlp-ao", .data =3D > &vlpcfg_ao_reg_mcd }, > + { .compatible =3D "mediatek,mt8189-vlpcfg-ao", .data =3D > &vlpcfg_reg_mcd }, > + { /* sentinel */ } > +}; > + > +static struct platform_driver clk_mt8189_vlpcfg_drv =3D { > + .probe =3D mtk_clk_simple_probe, > + .remove =3D mtk_clk_simple_remove, > + .driver =3D { > + .name =3D "clk-mt8189-vlpcfg", > + .of_match_table =3D of_match_clk_mt8189_vlpcfg, > + }, > +}; > + > +module_platform_driver(clk_mt8189_vlpcfg_drv); > +MODULE_DESCRIPTION("MediaTek MT8189 vlpcfg clocks driver"); > +MODULE_LICENSE("GPL");