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Wed, 14 Oct 2026 04:18:19 +0000 (GMT) Received: from [9.124.213.187] (unknown [9.124.213.187]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 14 Oct 2026 04:18:19 +0000 (GMT) Message-ID: Date: Wed, 14 Oct 2026 09:48:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs To: Srikar Dronamraju , Tim Chen Cc: christophe.leroy@csgroup.eu, linux-kernel@vger.kernel.org, ritesh.list@gmail.com, kprateek.nayak@amd.com, yu.c.chen@intel.com, vineethr@linux.ibm.com, vincent.guittot@linaro.org, npiggin@gmail.com, mpe@ellerman.id.au, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, peterz@infradead.org References: <20261012102037.2477378-1-sshegde@linux.ibm.com> <0cbd60fcf328ffcb317739f60d327da3af6145f1.camel@linux.intel.com> <4d0f2f4631f2f836bb1aec140c2c8e3e11d7ba20.camel@linux.intel.com> <5f107344-7ddf-402e-809c-7229ff6fb6d5@linux.ibm.com> Content-Language: en-US From: Shrikanth Hegde In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDAxNiBTYWx0ZWRfX0uDjNjO5J3cW Un+IVWVmX55fJXgAwGxwI0cW03YzGppKzi415WIgtDNev1M4njz9OiE4s3kpUWQOnMVz8qkGjBr H2cFajPEL1CsZmTGD2i5QViYJQbBebs= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDAxNiBTYWx0ZWRfXySXZhbBAfHTL QZCQDM/jHw9ub6X60WwZjNpB1O5xX7/MDJR/w3eiYjeuKd3leA44qjMlWkpZA8FHq81XGJArWfD 90dZfA9cExYsL4uv42l0LHbce0GMYJr4zfl1V97hvfLcEonYysFqR6+AXHzoQf30qtlfwp0bQ+z ib/AILNwB348nN90aW6ncCc8OMy8608CyJGH7rHpHL3vE9ziKTXGLPchYyrPSDI5zFELzw2G4A0 LOo28zj8dtHueZ616g+LtXIljxhCR0h/f692AAbHGepd4q8KDMymDkGizBeYVAVwjpK/KDftxB5 fFOArOgIxQmWZooPUxp/AxuJ2Vw5BFShgS63zKw0hRKh+NwrJA0Vrv8If8LhpAZKD8aZ1IpyojY vgs4y8nY67JmI12P0fvPp9ERJkHjzzjkhjXgUvtiFa0X+GWZTUrNPjJ7UAVISiwcXF4WxMoFfOB berwd9gotI00f0M/7QA== X-Proofpoint-GUID: edQIIEEYGG0lSQo0Q3kbLKCBMxeawP0p X-Authority-Analysis: v=2.4 cv=RoFQvymK c=1 sm=1 tr=0 ts=6acf0293 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=1qPKxZ1lXodfsSuZhD4A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: k6d73xMwrmR2h8MeWaLV3IH7LnORcOFn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140016 On 10/14/26 9:26 AM, Srikar Dronamraju wrote: > * Shrikanth Hegde [2026-10-14 08:46:11]: > >> On 10/14/26 2:14 AM, Tim Chen wrote: >>> On Tue, 2026-10-13 at 15:28 +0530, Shrikanth Hegde wrote: >>>> >>> >>> - SMT: patch 3 adds SD_SHARE_LLC only to MC/PKG, so for "smt" the >>> flags are as before. I think it is possible for P9 to have >>> shared_caches between two cores: >>> >>> /* >>> * P9 has a slightly odd architecture where pairs of cores share an L2 cache. >>> * This topology makes it *much* cheaper to migrate tasks between adjacent cores >>> * since the migrated task remains cache hot. We want to take advantage of this >>> * at the scheduler level so an extra topology level is required. >>> */ >>> >>> the CACHE level also has SD_SHARE_LLC, and highest_flag_domain() picks it, so sd_llc spans >>> cpu_l2_cache_map. shared_caches is only set when that map is wider >>> than the core's threads, e.g. a P9 core pair sharing an L2: >>> >>> CPU: 0 1 2 3 | 4 5 6 7 >>> cpu_smt_mask(): core A | core B >>> sd_llc (CACHE): 0-7 >>> >>> The ids follow cpu_smt_mask(), so 0-3 and 4-7 get different ids >>> while sd_llc and sd_llc_size cover all eight, and >>> cpus_share_cache(0, 4) is false, which is incorrect. >>> >> >> Yes. I doubt anyone wants to try this experiment on Power9. >> But yes, functionally updating the flags is needed. >> >> @srikar, >> That is also the reason for having the disabled. By default on P9, >> llc will be at CACHE domain. But, one may want to experiment with =smt >> which i doubt anyone will ever do. >> > > I think P9 is a very valid point, but I don't think we should look at disable > as an option just for this. > > I would say, lets keep it simple now, just have an option rather a toggle to > have LLC as MC/PKG for experimentation purpose. Switch the toggle and it > does back to regular LLC mode. Also we don't know how the future Power > Systems LLCs will look like. So keeping it a simple toggle, will reduce pain > and increase our flexibility for the future. > > Whether the toggle will switch to MC or PKG could be decided based on the > experiment results. > Ok. So kernel parameter "llc_override=mc/pkg" exclusively for ppc. llc_override=mc means LLC is at MC. llc_override=pkg means LLC is at PKG. No kernel parameter means no change. Hope that sounds good. Also this new kernel parameter sounds a distant relative of split_llc.