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Wed, 12 Feb 2025 23:05:25 -0800 (PST) Message-ID: Date: Thu, 13 Feb 2025 07:05:22 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/2] spi: s3c64xx: add support for samsung,exynos990-spi To: Denzeel Oliva , andi.shyti@kernel.org, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, peter.griffin@linaro.org, andre.draszik@linaro.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250212191241.280-1-wachiturroxd150@gmail.com> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <20250212191241.280-1-wachiturroxd150@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi! On 2/12/25 7:12 PM, Denzeel Oliva wrote: > The Exynos990 SPI controller shares similarities with > the GS101 (Google Tensor) SPI implementation, > but introduces specific hardware requirements such as > 32-bit register access and variable FIFO depths depending on gs101 mandates 32-bit accesses too. > the SPI node where it will have to be specified in DT (Device Tree). gs101 has some USI nodes that can work only in uart mode and indeed the fifosize there is 256. Does downstream define SPI nodes with 256 bytes FIFOs? Can you please point me the the downstream code? Cheers, ta > > Denzeel Oliva (2): > spi: dt-bindings: samsung: add samsung,exynos990-spi compatible > spi: s3c64xx: add support exynos990-spi to new port config data > > .../devicetree/bindings/spi/samsung,spi.yaml | 1 + > drivers/spi/spi-s3c64xx.c | 17 +++++++++++++++++ > 2 files changed, 18 insertions(+) >