From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9F42724167A; Mon, 20 Oct 2025 10:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760956487; cv=none; b=IL44IIg78QK+pAJM/zpZweXkdPUutWu8UpNQA8u2d0qiGpXsiihcbJ1YshIRMYGcHmFtWU+Po9SQGTGVyeMx2htQ5yocMPleF02ncxCcFMsIjv8hhBlxY88Lkol+Y/QGB+Ae9qsqAeAQsBzF2qYkZImBGCuWEC0UMkHemTCTStw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760956487; c=relaxed/simple; bh=c2OU16wGnrVpMzoppH1IWuhNPGGBG4O+QaZbd3WqpPw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=GHYjr1mOtoZSFJiwbxttV8+J9iei85bF+ZObk6BBAtra+ul7+NAysK/JZkJNai5bMRO0r4ZTaE3m78zeIq6tEzY/k6zjIlmMFTYAkkM9Ome5fKU5X2gzrekqwcHinK9y+nXkNiTgFKYHRl0oI9WDYV4otbgSvvRb+BJL75DT3M0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C2AC1063; Mon, 20 Oct 2025 03:34:37 -0700 (PDT) Received: from [10.1.196.46] (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6BA783F63F; Mon, 20 Oct 2025 03:34:40 -0700 (PDT) Message-ID: Date: Mon, 20 Oct 2025 11:34:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/29] ACPI / PPTT: Find cache level by cache-id To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Jeremy Linton , Gavin Shan References: <20251017185645.26604-1-james.morse@arm.com> <20251017185645.26604-4-james.morse@arm.com> From: Ben Horgan Content-Language: en-US In-Reply-To: <20251017185645.26604-4-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi James, On 10/17/25 19:56, James Morse wrote: > The MPAM table identifies caches by id. The MPAM driver also wants to know > the cache level to determine if the platform is of the shape that can be > managed via resctrl. Cacheinfo has this information, but only for CPUs that > are online. > > Waiting for all CPUs to come online is a problem for platforms where > CPUs are brought online late by user-space. > > Add a helper that walks every possible cache, until it finds the one > identified by cache-id, then return the level. > > Signed-off-by: James Morse > Reviewed-by: Fenghua Yu > Reviewed-by: Gavin Shan > Tested-by: Fenghua Yu > --- > Changes sinec v2: > * Search all caches, not just unified caches. This removes the need to count > the caches first, but means a failure to find the table walks the table > three times for different cache types. > * Fixed return value of the no-acpi stub. > * Punctuation typo in a comment, > * Keep trying to parse the table even if a bogus CPU is encountered. > * Specified CPUs share caches with other CPUs. > > Changes since v1: > * Droppeed the cleanup based table freeing, use acpi_get_pptt() instead. > * Removed a confusing comment. > * Clarified the kernel doc. > > Changes since RFC: > * acpi_count_levels() now returns a value. > * Converted the table-get stuff to use Jonathan's cleanup helper. > * Dropped Sudeep's Review tag due to the cleanup change. > --- > drivers/acpi/pptt.c | 82 ++++++++++++++++++++++++++++++++++++++++++++ > include/linux/acpi.h | 5 +++ > 2 files changed, 87 insertions(+) > > diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c > index 63c3a344c075..50c8f2a3c927 100644 > --- a/drivers/acpi/pptt.c > +++ b/drivers/acpi/pptt.c > @@ -350,6 +350,27 @@ static struct acpi_pptt_cache *acpi_find_cache_node(struct acpi_table_header *ta > return found; > } > > +static struct acpi_pptt_cache * > +acpi_find_any_type_cache_node(struct acpi_table_header *table_hdr, > + u32 acpi_cpu_id, unsigned int level, > + struct acpi_pptt_processor **node) > +{ > + struct acpi_pptt_cache *cache; > + > + cache = acpi_find_cache_node(table_hdr, acpi_cpu_id, CACHE_TYPE_UNIFIED, > + level, node); > + if (cache) > + return cache; > + > + cache = acpi_find_cache_node(table_hdr, acpi_cpu_id, CACHE_TYPE_DATA, > + level, node); > + if (cache) > + return cache; > + > + return acpi_find_cache_node(table_hdr, acpi_cpu_id, CACHE_TYPE_INST, > + level, node); > +} > + > /** > * update_cache_properties() - Update cacheinfo for the given processor > * @this_leaf: Kernel cache info structure being updated > @@ -903,3 +924,64 @@ void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus) > entry->length); > } > } > + > +/* > + * find_acpi_cache_level_from_id() - Get the level of the specified cache > + * @cache_id: The id field of the cache > + * > + * Determine the level relative to any CPU for the cache identified by > + * cache_id. This allows the property to be found even if the CPUs are offline. > + * > + * The returned level can be used to group caches that are peers. > + * > + * The PPTT table must be rev 3 or later. > + * > + * If one CPU's L2 is shared with another CPU as L3, this function will return > + * an unpredictable value. > + * > + * Return: -ENOENT if the PPTT doesn't exist, the revision isn't supported or > + * the cache cannot be found. > + * Otherwise returns a value which represents the level of the specified cache. > + */ > +int find_acpi_cache_level_from_id(u32 cache_id) > +{ > + int level, cpu; > + u32 acpi_cpu_id; > + struct acpi_pptt_cache *cache; > + struct acpi_table_header *table; > + struct acpi_pptt_cache_v1 *cache_v1; > + struct acpi_pptt_processor *cpu_node; > + > + table = acpi_get_pptt(); > + if (!table) > + return -ENOENT; > + > + if (table->revision < 3) > + return -ENOENT; > + > + for_each_possible_cpu(cpu) { > + acpi_cpu_id = get_acpi_id_for_cpu(cpu); > + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); > + if (!cpu_node) > + continue; > + > + /* Start at 1 for L1 */ > + level = 1; > + cache = acpi_find_any_type_cache_node(table, acpi_cpu_id, level, > + &cpu_node); > + while (cache) { > + cache_v1 = ACPI_ADD_PTR(struct acpi_pptt_cache_v1, > + cache, sizeof(*cache)); > + > + if (cache->flags & ACPI_PPTT_CACHE_ID_VALID && > + cache_v1->cache_id == cache_id) > + return level; > + > + level++; If there is more than one type of cache at a given level only one is checked. For example, if there is an L1 data cache and an L1 instruction cache then the L1 instruction cache will never be considered. > + cache = acpi_find_any_type_cache_node(table, acpi_cpu_id, > + level, &cpu_node); > + } > + } > + > + return -ENOENT; > +} Thanks, Ben