From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751719AbdLNLlO (ORCPT ); Thu, 14 Dec 2017 06:41:14 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45500 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751164AbdLNLlM (ORCPT ); Thu, 14 Dec 2017 06:41:12 -0500 Subject: Re: [PATCH V2] KVM/x86: Check input paging mode when cs.l is set To: Lan Tianyu Cc: rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, dvyukov@google.com, jmattson@google.com References: <1513223753-551-1-git-send-email-tianyu.lan@intel.com> From: Paolo Bonzini Message-ID: Date: Thu, 14 Dec 2017 12:41:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <1513223753-551-1-git-send-email-tianyu.lan@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 14 Dec 2017 11:41:12 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/12/2017 04:55, Lan Tianyu wrote: > + * When EFER.LME and CR0.PG are set, CR4.PAE and EFER.LMA > + * must be set. > + */ > + if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG_BIT)) { > + if (!(sregs->cr4 & X86_CR4_PAE_BIT)) > + return -EINVAL; > + if (!(sregs->efer & EFER_LMA)) > + return -EINVAL; > + } else if (sregs->efer & EFER_LMA) This can just be "(sregs->efer & EFER_LMA) || sregs->cs.l", making the next "if" redundant. Even better written as if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG_BIT)) { /* * When EFER.LME and CR0.PG are set, the processor is in * 64-bit mode (though maybe in a 32-bit code segment). * CR4.PAE and EFER.LMA must be set. */ if (... || ...) return -EINVAL; } else { /* * Not in 64-bit mode: EFER.LMA is clear and the code * segment cannot be 64-bit. */ if (... || ...) return -EINVAL; } Paolo > + return -EINVAL; > + > + /* When CS.L is set, vcpu should run in 64-bit mode. */ > + if (sregs->cs.l) > + if (!((sregs->cr0 & X86_CR0_PG_BIT) && > + (sregs->cr4 & X86_CR4_PAE_BIT) && > + (sregs->efer & EFER_LME))) > + return -EINVAL;