From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753594AbdKGFpK (ORCPT ); Tue, 7 Nov 2017 00:45:10 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:20302 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753546AbdKGFpJ (ORCPT ); Tue, 7 Nov 2017 00:45:09 -0500 Subject: Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA To: Martin Blumenstingl References: <20171106075212.14275-1-yixun.lan@amlogic.com> <889b8fd5-31e4-1371-6121-0f1aec6fa777@baylibre.com> CC: , Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , , , Kevin Hilman , Carlo Caione , , , Xingyu Chen From: Yixun Lan Message-ID: Date: Tue, 7 Nov 2017 13:44:38 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.20.76] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin On 11/07/17 06:03, Martin Blumenstingl wrote: > Hi Yixun, > > On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote: >> Hi Neil: >> >> >> On 11/06/17 16:57, Neil Armstrong wrote: >>> On 06/11/2017 08:52, Yixun Lan wrote: >>>> According to the datasheet, in Meson-GXBB/GXL series, >>>> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >>>> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >>>> >>>> Test passed at gxl_skt dev board. >>>> >>>> Tested-by: Xingyu Chen >>>> Signed-off-by: Yixun Lan >>>> >>>> --- >>>> I think this error was introduced by a copy & paste from meson8 code? >>>> and we didn't notice them due to the SANA clock is also enabled by >>>> DTS (so SAR_ADC works fine)? >>>> --- >>>> drivers/clk/meson/gxbb.c | 4 ++-- >>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c >>>> index b2d1e8ed7152..92168348ffa6 100644 >>>> --- a/drivers/clk/meson/gxbb.c >>>> +++ b/drivers/clk/meson/gxbb.c >>>> @@ -1139,7 +1139,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); >>>> static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); >>>> static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); >>>> static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); >>>> -static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); >>>> +static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); >>>> static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); >>>> static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); >>>> static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); >>>> @@ -1190,7 +1190,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); >>>> static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); >>>> static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); >>>> static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); >>>> -static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); >>>> +static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); >>>> static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); >>>> static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); >>>> static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); >>>> >>> >>> Hi Yixun, >>> >>> Can you precise how it affects the saradc driver ? from the DT and clk PoV ? >>> >> the saradc module doesn't require sana clock (it's irrelvevant), we will >> send a patchset v3 to address this. > is the SANA clock irrelevant for the SAR ADC on all SoCs (even > Meson8/Meson8b/Meson8m2) or just on the GX SoCs? > also, do you know what "SANA" stands for? > > > Regards > Martin > > . > the sana clock irrelevant for all SoCs (including meson8/8b/8m2) SANA stands for Stream Analyzer