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Tue, 22 Aug 2023 11:46:33 GMT Received: from [10.216.34.168] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 22 Aug 2023 04:46:27 -0700 Message-ID: Date: Tue, 22 Aug 2023 17:16:18 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH 1/4] dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000 To: Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson CC: Taniya Das , , , , , Ajit Pandey , Jagadeesh Kona References: <20230808051407.647395-1-quic_imrashai@quicinc.com> <20230808051407.647395-2-quic_imrashai@quicinc.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XRvnFqoX-bqaMeO3OD1wydwDpceiFF4q X-Proofpoint-ORIG-GUID: XRvnFqoX-bqaMeO3OD1wydwDpceiFF4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_10,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220089 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/16/2023 11:19 AM, Krzysztof Kozlowski wrote: > On 08/08/2023 07:14, Imran Shaik wrote: >> Add device tree bindings for qcom ecpri clock controller on QDU1000 and >> QRU1000 SoCs. >> >> Signed-off-by: Imran Shaik >> --- >> .../bindings/clock/qcom,qdu1000-ecpricc.yaml | 68 +++++++ >> .../dt-bindings/clock/qcom,qdu1000-ecpricc.h | 192 ++++++++++++++++++ >> 2 files changed, 260 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,qdu1000-ecpricc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml >> new file mode 100644 >> index 000000000000..db54052bf360 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml >> @@ -0,0 +1,68 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000 >> + >> +maintainers: >> + - Taniya Das >> + - Imran Shaik >> + >> +description: | >> + Qualcomm ecpri clock control module which supports the clocks, resets >> + on QDU1000 and QRU1000 >> + >> + See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,qdu1000-ecpricc >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: GPLL0 source from GCC >> + - description: GPLL1 source from GCC >> + - description: GPLL2 source from GCC >> + - description: GPLL3 source from GCC >> + - description: GPLL4 source from GCC >> + - description: GPLL5 source from GCC >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + reg: >> + maxItems: 1 > > Keep the same order as in required: below. > > Reviewed-by: Krzysztof Kozlowski > > Best regards, > Krzysztof > Sure, will update this in next series. Thanks, Imran