From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Herve Codina <herve.codina@bootlin.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Nicolin Chen <nicoleotsuka@gmail.com>,
Randy Dunlap <rdunlap@infradead.org>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v2 04/28] soc: fsl: cpm1: qmc: Extend the API to provide Rx status
Date: Tue, 8 Aug 2023 07:41:56 +0000 [thread overview]
Message-ID: <bb8337b2-807e-9cc3-6835-1bcb7e7eca58@csgroup.eu> (raw)
In-Reply-To: <20230726150225.483464-5-herve.codina@bootlin.com>
Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In HDLC mode, some status flags related to the data read transfer can be
> set by the hardware and need to be known by a QMC consumer for further
> analysis.
>
> Extend the API in order to provide these transfer status flags at the
> read complete() call.
>
> In TRANSPARENT mode, these flags have no meaning. Keep only one read
> complete() API and update the consumers working in transparent mode.
> In this case, the newly introduced flags parameter is simply unused.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> drivers/soc/fsl/qe/qmc.c | 29 +++++++++++++++++++++++++----
> include/soc/fsl/qe/qmc.h | 15 ++++++++++++++-
> sound/soc/fsl/fsl_qmc_audio.c | 2 +-
> 3 files changed, 40 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 8dc73cc1a83b..2d2a9d88ba6c 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -166,7 +166,7 @@
> struct qmc_xfer_desc {
> union {
> void (*tx_complete)(void *context);
> - void (*rx_complete)(void *context, size_t length);
> + void (*rx_complete)(void *context, size_t length, unsigned int flags);
> };
> void *context;
> };
> @@ -421,7 +421,8 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
> }
>
> int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> - void (*complete)(void *context, size_t length), void *context)
> + void (*complete)(void *context, size_t length, unsigned int flags),
> + void *context)
> {
> struct qmc_xfer_desc *xfer_desc;
> unsigned long flags;
> @@ -454,6 +455,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> xfer_desc->rx_complete = complete;
> xfer_desc->context = context;
>
> + /* Clear previous status flags */
> + ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO |
> + QMC_BD_RX_AB | QMC_BD_RX_CR);
> +
> /* Activate the descriptor */
> ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB);
> wmb(); /* Be sure to flush data before descriptor activation */
> @@ -485,7 +490,7 @@ EXPORT_SYMBOL(qmc_chan_read_submit);
>
> static void qmc_chan_read_done(struct qmc_chan *chan)
> {
> - void (*complete)(void *context, size_t size);
> + void (*complete)(void *context, size_t size, unsigned int flags);
> struct qmc_xfer_desc *xfer_desc;
> unsigned long flags;
> cbd_t __iomem *bd;
> @@ -527,7 +532,23 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
>
> if (complete) {
> spin_unlock_irqrestore(&chan->rx_lock, flags);
> - complete(context, datalen);
> +
> + /*
> + * Avoid conversion between internal hardware flags and
> + * the software API flags.
> + * -> Be sure that the software API flags are consistent
> + * with the hardware flags
> + */
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST != QMC_BD_RX_L);
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST != QMC_BD_RX_F);
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF != QMC_BD_RX_LG);
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA != QMC_BD_RX_NO);
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT != QMC_BD_RX_AB);
> + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC != QMC_BD_RX_CR);
> +
> + complete(context, datalen,
> + ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG |
> + QMC_BD_RX_NO | QMC_BD_RX_AB | QMC_BD_RX_CR));
> spin_lock_irqsave(&chan->rx_lock, flags);
> }
>
> diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
> index 3c61a50d2ae2..6f1d6cebc9fe 100644
> --- a/include/soc/fsl/qe/qmc.h
> +++ b/include/soc/fsl/qe/qmc.h
> @@ -9,6 +9,7 @@
> #ifndef __SOC_FSL_QMC_H__
> #define __SOC_FSL_QMC_H__
>
> +#include <linux/bits.h>
> #include <linux/types.h>
>
> struct device_node;
> @@ -56,8 +57,20 @@ int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param
> int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> void (*complete)(void *context), void *context);
>
> +/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
> + * No flags are available in transparent mode and the read complete() flags
> + * parameter has no meaning in transparent mode.
> + */
> +#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */
> +#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */
> +#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */
> +#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not multiple of 8) */
> +#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seven consecutive ones) */
> +#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */
> +
> int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
> - void (*complete)(void *context, size_t length),
> + void (*complete)(void *context, size_t length,
> + unsigned int flags),
> void *context);
>
> #define QMC_CHAN_READ (1<<0)
> diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
> index 7cbb8e4758cc..5d745aae17a8 100644
> --- a/sound/soc/fsl/fsl_qmc_audio.c
> +++ b/sound/soc/fsl/fsl_qmc_audio.c
> @@ -99,7 +99,7 @@ static void qmc_audio_pcm_write_complete(void *context)
> snd_pcm_period_elapsed(prtd->substream);
> }
>
> -static void qmc_audio_pcm_read_complete(void *context, size_t length)
> +static void qmc_audio_pcm_read_complete(void *context, size_t length, unsigned int flags)
> {
> struct qmc_dai_prtd *prtd = context;
> int ret;
next prev parent reply other threads:[~2023-08-08 16:59 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 15:01 [PATCH v2 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Herve Codina
2023-07-26 15:01 ` [PATCH v2 01/28] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration Herve Codina
2023-08-08 7:40 ` Christophe Leroy
2023-07-26 15:01 ` [PATCH v2 02/28] soc: fsl: cpm1: qmc: " Herve Codina
2023-08-08 7:40 ` Christophe Leroy
2023-07-26 15:01 ` [PATCH v2 03/28] soc: fsl: cpm1: qmc: Fix rx channel reset Herve Codina
2023-08-08 7:41 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 04/28] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Herve Codina
2023-08-08 7:41 ` Christophe Leroy [this message]
2023-07-26 15:02 ` [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC Herve Codina
2023-07-27 8:19 ` Conor Dooley
2023-07-27 9:09 ` Herve Codina
2023-07-27 9:53 ` Conor Dooley
2023-07-27 10:34 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 06/28] net: wan: " Herve Codina
2023-08-01 9:31 ` Andrew Lunn
2023-08-01 10:07 ` Herve Codina
2023-08-08 8:02 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 07/28] MAINTAINERS: Add the Freescale QMC HDLC driver entry Herve Codina
2023-07-26 15:02 ` [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks Herve Codina
2023-08-01 9:33 ` Andrew Lunn
2023-08-01 10:05 ` Herve Codina
2023-08-08 8:04 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 09/28] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Herve Codina
2023-08-08 8:04 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 10/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Herve Codina
2023-08-01 9:36 ` Andrew Lunn
2023-08-01 10:23 ` Herve Codina
2023-08-08 8:05 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 11/28] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Herve Codina
2023-08-08 8:05 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 12/28] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Herve Codina
2023-08-08 8:06 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 13/28] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Herve Codina
2023-08-08 8:06 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 14/28] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Herve Codina
2023-08-08 8:08 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 15/28] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Herve Codina
2023-08-08 8:09 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 16/28] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Herve Codina
2023-08-08 8:09 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 17/28] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Herve Codina
2023-08-08 8:10 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 18/28] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Herve Codina
2023-08-08 8:10 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 19/28] wan: qmc_hdlc: Add runtime timeslots changes support Herve Codina
2023-08-08 8:11 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 20/28] net: wan: Add framer framework support Herve Codina
2023-08-01 9:56 ` Andrew Lunn
2023-08-01 10:32 ` Herve Codina
2023-08-08 8:11 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Herve Codina
2023-08-01 10:05 ` Andrew Lunn
2023-08-01 10:35 ` Herve Codina
2023-08-03 0:40 ` Rob Herring
2023-08-03 8:11 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting Herve Codina
2023-07-27 9:22 ` Lee Jones
2023-07-27 10:18 ` Herve Codina
2023-08-08 8:13 ` Christophe Leroy
2023-08-08 8:44 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer Herve Codina
2023-08-01 10:22 ` Andrew Lunn
2023-08-01 10:44 ` Herve Codina
2023-08-01 10:52 ` Andrew Lunn
2023-08-01 11:12 ` Herve Codina
2023-08-08 8:15 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux Herve Codina
2023-08-07 13:05 ` Linus Walleij
2023-08-07 13:06 ` Linus Walleij
2023-08-07 13:17 ` Andrew Lunn
2023-08-07 14:36 ` Herve Codina
2023-08-07 13:09 ` Mark Brown
2023-08-08 9:00 ` Linus Walleij
2023-08-07 14:27 ` Herve Codina
2023-08-08 8:16 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 25/28] MAINTAINERS: Add the Lantiq PEF2256 driver entry Herve Codina
2023-08-08 8:17 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec Herve Codina
2023-08-01 10:30 ` Andrew Lunn
2023-08-01 10:45 ` Herve Codina
2023-08-08 8:26 ` Christophe Leroy
2023-08-08 9:06 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support Herve Codina
2023-07-27 8:12 ` Conor Dooley
2023-07-27 9:19 ` Herve Codina
2023-08-03 0:42 ` Rob Herring
2023-08-03 8:23 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 28/28] net: wan: fsl_qmc_hdlc: " Herve Codina
2023-08-08 8:29 ` Christophe Leroy
2023-08-01 10:34 ` [PATCH v2 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Andrew Lunn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bb8337b2-807e-9cc3-6835-1bcb7e7eca58@csgroup.eu \
--to=christophe.leroy@csgroup.eu \
--cc=Xiubo.Lee@gmail.com \
--cc=alsa-devel@alsa-project.org \
--cc=andrew@lunn.ch \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=festevam@gmail.com \
--cc=herve.codina@bootlin.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kuba@kernel.org \
--cc=lee@kernel.org \
--cc=leoyang.li@nxp.com \
--cc=lgirdwood@gmail.com \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=netdev@vger.kernel.org \
--cc=nicoleotsuka@gmail.com \
--cc=pabeni@redhat.com \
--cc=perex@perex.cz \
--cc=qiang.zhao@nxp.com \
--cc=rdunlap@infradead.org \
--cc=robh+dt@kernel.org \
--cc=shengjiu.wang@gmail.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=tiwai@suse.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®