From: Vignesh Raghavendra <vigneshr@ti.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Marek Vasut <marek.vasut@gmail.com>,
Richard Weinberger <richard@nod.at>,
Rob Herring <robh+dt@kernel.org>
Cc: <linux-mtd@lists.infradead.org>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Joakim Tjernlund <Joakim.Tjernlund@infinera.com>,
<devicetree@vger.kernel.org>,
Mason Yang <masonccyang@mxic.com.tw>,
<linux-arm-kernel@lists.infradead.org>, <nsekhar@ti.com>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 4/5] dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller
Date: Wed, 17 Apr 2019 12:12:18 +0530 [thread overview]
Message-ID: <bba45d90-93dd-39c3-1b13-5326956bed89@ti.com> (raw)
In-Reply-To: <6a69ce6f-66c0-3f7c-a326-d76ee717cacf@cogentembedded.com>
On 14/04/19 11:25 PM, Sergei Shtylyov wrote:
> On 04/12/2019 12:29 PM, Vignesh Raghavendra wrote:
>
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
>> ---
>> .../devicetree/bindings/mtd/ti,am654-hbmc.txt | 31 +++++++++++++++++++
>> MAINTAINERS | 1 +
>> 2 files changed, 32 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
>> new file mode 100644
>> index 000000000000..00888482df25
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
>> @@ -0,0 +1,31 @@
> [...]
>> +Optional properties:
>> +- mux-controls: phandle to the multiplexer that controls selection of
>> + HBMC vs OSPI. Mux state of 1 indicates HBMC is selected.
>
> I thought this is usually done with the help of drivers/pinctrl/..
>
This mux is internal to SoC and not at SoC pad level. Based on this bit
read/write requests at SoC interconnect is routed either to OSPI or
HBMC, hence mmio-mux is a good fit
OSPI and HBMC data pins are themselves at pad level which is handled by
pinctrl-single node.
>> +
>> +Example:
>> + hbmc: hbmc@47034000 {
>> + compatible = "ti,am654-hbmc";
>> + reg = <0x0 0x47034000 0x0 0x100>,
>> + <0x5 0x00000000 0x1 0x0000000>;
>> + power-domains = <&k3_pds 55>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
>> + <0x1 0x5 0x04000000 0x4000000>; /* CS1 - 64MB
>> +
>> + /* Slave flash node */
>> + flash@0{
>
> Need space before {.
>
Will fix.
>> + compatible = "cypress,hyperflash";
>> + reg = <0x0 0x4000000>;
>> + };
>> + };
> [...]
>
> MBR, Sergei
>
--
Regards
Vignesh
next prev parent reply other threads:[~2019-04-17 6:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-12 9:29 [PATCH v3 0/5] MTD: Add Initial Hyperbus support Vignesh Raghavendra
2019-04-12 9:29 ` [PATCH v3 1/5] mtd: cfi_cmdset_0002: Add support for polling status register Vignesh Raghavendra
2019-04-12 9:29 ` [PATCH v3 2/5] dt-bindings: mtd: Add binding documentation for HyperFlash Vignesh Raghavendra
2019-04-12 9:29 ` [PATCH v3 3/5] mtd: Add support for HyperBus memory devices Vignesh Raghavendra
2019-04-14 17:51 ` Sergei Shtylyov
2019-04-17 6:42 ` Vignesh Raghavendra
2019-04-12 9:29 ` [PATCH v3 4/5] dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller Vignesh Raghavendra
2019-04-14 17:55 ` Sergei Shtylyov
2019-04-17 6:42 ` Vignesh Raghavendra [this message]
2019-04-12 9:29 ` [PATCH v3 5/5] mtd: hyperbus: Add driver for TI's " Vignesh Raghavendra
2019-04-17 17:24 ` [PATCH v3 0/5] MTD: Add Initial Hyperbus support Vignesh Raghavendra
2019-04-18 16:39 ` Sergei Shtylyov
2019-04-23 6:06 Vignesh Raghavendra
2019-04-23 6:06 ` [PATCH v3 4/5] dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller Vignesh Raghavendra
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