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[86.30.250.44]) by smtp.googlemail.com with ESMTPSA id y80sm2308211wmc.34.2020.06.09.02.18.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jun 2020 02:18:36 -0700 (PDT) Subject: Re: [PATCH 2/5] soundwire: qcom: add support for mmio soundwire devices To: Vinod Koul , Jonathan Marek Cc: alsa-devel@alsa-project.org, Andy Gross , Bjorn Andersson , Sanyog Kale , Pierre-Louis Bossart , "open list:ARM/QUALCOMM SUPPORT" , open list References: <20200608204347.19685-1-jonathan@marek.ca> <20200608204347.19685-3-jonathan@marek.ca> <20200609043420.GA1084979@vkoul-mobl> From: Srinivas Kandagatla Message-ID: Date: Tue, 9 Jun 2020 10:18:35 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20200609043420.GA1084979@vkoul-mobl> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/06/2020 05:34, Vinod Koul wrote: > Hi Jonathan, > > On 08-06-20, 16:43, Jonathan Marek wrote: >> Adds support for qcom soundwire devices with memory mapped IO registers. > > Please use 'SoundWire Master devices' instead :) > >> >> Signed-off-by: Jonathan Marek >> --- >> drivers/soundwire/qcom.c | 25 +++++++++++++++++++++++-- >> 1 file changed, 23 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c >> index f38d1fd3679f..628747df1c75 100644 >> --- a/drivers/soundwire/qcom.c >> +++ b/drivers/soundwire/qcom.c >> @@ -90,6 +90,7 @@ struct qcom_swrm_ctrl { >> struct sdw_bus bus; >> struct device *dev; >> struct regmap *regmap; >> + void __iomem *mmio; >> struct completion *comp; >> struct work_struct slave_work; >> /* read/write lock */ >> @@ -154,6 +155,20 @@ static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, >> return SDW_CMD_OK; >> } >> >> +static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, >> + u32 *val) >> +{ >> + *val = readl(ctrl->mmio + reg); >> + return SDW_CMD_OK; >> +} >> + >> +static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, >> + int val) >> +{ >> + writel(val, ctrl->mmio + reg); >> + return SDW_CMD_OK; >> +} > > this looks fine but regmap supports mmio also, so I am thinking we > should remove these and set regmap (mmio/slim)... Srini..? That is doable, but not going to add great value in this case, unless we are having another layer of abstraction. So keeping it as readl/writel seems okay to me. --srini >