From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6047EC43381 for ; Wed, 6 Mar 2019 17:02:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3379620684 for ; Wed, 6 Mar 2019 17:02:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730412AbfCFRCX (ORCPT ); Wed, 6 Mar 2019 12:02:23 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:25721 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726636AbfCFRCV (ORCPT ); Wed, 6 Mar 2019 12:02:21 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x26GuHKW022932; Wed, 6 Mar 2019 18:01:57 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2qyhgb16m0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 06 Mar 2019 18:01:57 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5968734; Wed, 6 Mar 2019 17:01:56 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 30C6950D7; Wed, 6 Mar 2019 17:01:56 +0000 (GMT) Received: from [10.48.0.237] (10.75.127.51) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 6 Mar 2019 18:01:55 +0100 Subject: Re: [PATCH 4/5] mmc: mmci: stm32: define get_dctrl_cfg To: Ulf Hansson CC: Rob Herring , Srinivas Kandagatla , Maxime Coquelin , Alexandre Torgue , Linux ARM , Linux Kernel Mailing List , DTML , "linux-mmc@vger.kernel.org" , References: <1551694625-6414-1-git-send-email-ludovic.Barre@st.com> <1551694625-6414-5-git-send-email-ludovic.Barre@st.com> From: Ludovic BARRE Message-ID: Date: Wed, 6 Mar 2019 18:01:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG6NODE1.st.com (10.75.127.16) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-06_11:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/6/19 2:31 PM, Ulf Hansson wrote: > On Mon, 4 Mar 2019 at 11:17, Ludovic Barre wrote: >> >> From: Ludovic Barre >> >> This patch defines get_dctrl_cfg callback for sdmmc variant. >> sdmmc variant has specific stm32 transfer modes. >> sdmmc data transfer mode selection could be: >> -Block data transfer ending on block count. >> -SDIO multibyte data transfer. >> -MMC Stream data transfer (not used). >> -Block data transfer ending with STOP_TRANSMISSION command. >> >> Signed-off-by: Ludovic Barre >> --- >> drivers/mmc/host/mmci.h | 5 +++++ >> drivers/mmc/host/mmci_stm32_sdmmc.c | 21 +++++++++++++++++++++ >> 2 files changed, 26 insertions(+) >> >> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h >> index 6f28f71..eb5d99af 100644 >> --- a/drivers/mmc/host/mmci.h >> +++ b/drivers/mmc/host/mmci.h >> @@ -131,6 +131,11 @@ >> /* Control register extensions in the Qualcomm versions */ >> #define MCI_DPSM_QCOM_DATA_PEND BIT(17) >> #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) >> +/* Control register extensions in STM32 versions */ >> +#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) >> +#define MCI_DPSM_STM32_MODE_SDIO (1 << 2) >> +#define MCI_DPSM_STM32_MODE_STREAM (2 << 2) >> +#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) >> >> #define MMCIDATACNT 0x030 >> #define MMCISTATUS 0x034 >> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c >> index cfbfc6f..e7bf744 100644 >> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c >> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c >> @@ -265,10 +265,31 @@ static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) >> } >> } >> >> +u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) >> +{ >> + struct variant_data *variant = host->variant; >> + int blksz_bits; >> + u32 datactrl; >> + >> + blksz_bits = ffs(host->data->blksz) - 1; >> + datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; >> + >> + if (host->mmc->card && mmc_card_sdio(host->mmc->card) && >> + host->data->blocks == 1) > > These settings are not limited to deal with the block size bits. > > Don't get me wrong, it seems reasonable to include them, but the > generic code in mmci_start_data() also have code to cope with SDIO. I > think we should start by splitting that up into a couple of > helper/library functions, and make the legacy variant to use them. > This should probably be done as a preparation to your series, so you > can build on top of that. I think you wish helper functions for each group of datactrl feature, like for dpsm direction|sdio|ios timming. Each variant call theses helpers to define its own datactrl value. it's possible, no problem. In mmci_start_data will remain the part on clk_reg for sdio card if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { u32 clk; /* * The ST Micro variant for SDIO small write transfers * needs to have clock H/W flow control disabled, * otherwise the transfer will not start. The threshold * depends on the rate of MCLK. */ if (variant->st_sdio && data->flags & MMC_DATA_WRITE && (host->size < 8 || (host->size <= 8 && host->mclk > 50000000))) clk = host->clk_reg & ~variant->clkreg_enable; else clk = host->clk_reg | variant->clkreg_enable; mmci_write_clkreg(host, clk); } it's OK ? > > Does it make sense? If not, please tell and I can try to provide some > patch to show you what I mean. > > >> + datactrl |= MCI_DPSM_STM32_MODE_SDIO; >> + else if (host->data->stop && !host->mrq->sbc) >> + datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; >> + else >> + datactrl |= MCI_DPSM_STM32_MODE_BLOCK; >> + >> + return datactrl; >> +} >> + >> static struct mmci_host_ops sdmmc_variant_ops = { >> .validate_data = sdmmc_idma_validate_data, >> .prep_data = sdmmc_idma_prep_data, >> .unprep_data = sdmmc_idma_unprep_data, >> + .get_datactrl_cfg = sdmmc_get_dctrl_cfg, >> .dma_setup = sdmmc_idma_setup, >> .dma_start = sdmmc_idma_start, >> .dma_finalize = sdmmc_idma_finalize, >> -- >> 2.7.4 >> > > Kind regards > Uffe >