From: Sander Vanheule <sander@svanheule.net>
To: Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Birger Koblitz <mail@birger-koblitz.de>,
Bert Vermeulen <bert@biot.com>, John Crispin <john@phrozen.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Frank Rowand <frowand.list@gmail.com>
Subject: realtek,rtl-intc IRQ mapping broken on 5.16-rc1
Date: Thu, 18 Nov 2021 16:56:06 +0100 [thread overview]
Message-ID: <bbe5506a2458b2d6049bd22a5fda77ae6175ddec.camel@svanheule.net> (raw)
Hi everyone,
On 5.16-rc1, the realtek,rtl-intc interrupt controller driver for Realtek RTL8380 SoCs
(and related) appears broken. When booting, I don't get a tty on the serial port, although
serial output works.
The watchdog (currently under review) also cannot acquire the required phase1 interrupt,
and produces the following output:
[ 1.968228] realtek-otto-watchdog 18003150.watchdog: error -EINVAL: Failed to get IRQ 4
for phase1
[ 1.978404] realtek-otto-watchdog: probe of 18003150.watchdog failed with error -22
A bisects points to commit 041284181226 ("of/irq: Allow matching of an interrupt-map local
to an interrupt controller"). Reverting this above commit and follow-up commit
10a20b34d735 ("of/irq: Don't ignore interrupt-controller when interrupt-map failed")
restores the functionality from v5.15.
Below you can find the DTS that I used to reproduce this on my Zyxel GS1900-8.
Best,
Sander
---
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "zyxel,gs1900-8", "realtek,rtl83xx-soc";
model = "ZyXEL GS1900-8";
aliases {
serial0 = &serial0;
};
baseclk: baseclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
chosen {
stdout-path = "serial0";
bootargs = "earlycon console=ttyS0,115200";
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips4KEc";
reg = <0>;
clocks = <&baseclk>;
clock-names = "cpu";
};
};
lx_clk: lx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
soc: soc@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
serial0: serial@2000 {
compatible = "ns16550a";
reg = <0x2000 0x100>;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <31>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
};
intc: interrupt-controller@3000 {
compatible = "realtek,rtl-intc";
reg = <0x3000 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <0>;
interrupt-map =
<31 &cpuintc 2>, /* UART0 */
<20 &cpuintc 3>, /* SWCORE */
<19 &cpuintc 4>, /* WDT IP1 */
<18 &cpuintc 5>; /* WDT IP2 */
};
watchdog@3150 {
compatible = "realtek,rtl8380-wdt";
reg = <0x3150 0xc>;
realtek,reset-mode = "soc";
clocks = <&lx_clk>;
timeout-sec = <20>;
interrupt-parent = <&intc>;
interrupt-names = "phase1", "phase2";
interrupts = <19>, <18>;
};
};
};
next reply other threads:[~2021-11-18 15:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-18 15:56 Sander Vanheule [this message]
2021-11-18 19:19 ` Marc Zyngier
2021-11-18 19:45 ` Sander Vanheule
2021-11-19 14:48 ` Marc Zyngier
2021-11-19 19:09 ` Birger Koblitz
2021-11-21 20:33 ` Sander Vanheule
2021-11-21 21:11 ` John Crispin
2021-11-22 10:33 ` Marc Zyngier
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