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Mon, 19 Oct 2026 23:03:26 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c409239a167sm448288766b.84.2026.10.19.23.03.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 23:03:25 -0700 (PDT) Message-ID: Date: Tue, 20 Oct 2026 08:03:23 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] soc: qcom: spm: don't clobber the SAW control registers To: Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Stephan Gerhold , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Ilia Lin Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev References: <20261019-fix-qcom-saw-v1-0-9c7ba3fc2493@oss.qualcomm.com> <20261019-fix-qcom-saw-v1-2-9c7ba3fc2493@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261019-fix-qcom-saw-v1-2-9c7ba3fc2493@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 2jvJhreYO80KrCQ4RIetxL-zJzrnRhG8 X-Authority-Analysis: v=2.4 cv=DZOCOftW c=1 sm=1 tr=0 ts=6ad70430 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=WNvXFvV67iztUfGrp4YA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: 2jvJhreYO80KrCQ4RIetxL-zJzrnRhG8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDAyMyBTYWx0ZWRfX3hqvYfel3rCo XC+KSCR+Ae1dkRbSKC3xsJoS2PJXNjcQNjI6NMlAKQz1sulKfR4DjE6D3ihh38iGcF8Iav7nVv6 vfbzyQBijzyYaYHJlcf0PYJWl5VCyO2MVjIOJiCdMqua1WUxIb80U8S7X6atbF9RF4TV6tCp775 n0DZrVF8HeUSFdsYUHPJuOXyDTGBnk04HFGWwmAIc6puEboIUVPRKnlLg7jLd776llaBpN6589X wKPwFl0rTIHT/8vJU/VNTH06ghTc6yWOqj3ZUOohI7vYu1ZlE7oGVTCg34TQYjfOK7BzY/ydPTk mu+xVb8DUaJs9g6vRbkh6oDNzdE5CpxpLJy85aTxFr5QUXUFqmm5zXdRvF9+9ILd+GUYIE1KPF6 huaibj5dBZdiLdA+gqSU5m210PA71hO34X7oOMQn53Vm9PK+18KP0lMWQh7vsAe4801nmjYJmec Qomuqo86e69Is2zhb+w== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDAyMyBTYWx0ZWRfX2Z4PjtU1ud3y j7Pm1qSvmz6qvnbk3tMs2q3d8ht7IO8L+WzCv2JnH/EZTJ2bjtWpA7mFjPjXUBT/FCEh9EgX0Wc pCH2ByGKjoo/HegvtJx+Z/jp/SCZdTI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200023 On 10/19/26 4:39 PM, Dmitry Baryshkov wrote: > The SAWv4.1 and SAWv2.3 register tables have no sequence entry, so > probe copies the all-zero sequence buffer to offset 0 instead, wiping > the SPM_CTL, SPM_DLY and SAW_CFG values the boot firmware programmed. > On MSM8998 the firmware then still powers the gold cluster down once > its last CPU goes offline, but never brings it back: PSCI CPU_ON leaves > the first CPU pending and the SoC hangs or resets. > > Only write the sequence when the SAW has a sequence entry, like the > other registers. > > Fixes: 13e72c3e2261 ("soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS") > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/soc/qcom/spm.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c > index d41c94d32b51..6f2f14eb9022 100644 > --- a/drivers/soc/qcom/spm.c > +++ b/drivers/soc/qcom/spm.c > @@ -528,9 +528,11 @@ static int spm_dev_probe(struct platform_device *pdev) > platform_set_drvdata(pdev, drv); > > /* Write the SPM sequences first.. */ > - addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; > - __iowrite32_copy(addr, drv->reg_data->seq, > - ARRAY_SIZE(drv->reg_data->seq) / 4); > + if (drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]) { > + addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; > + __iowrite32_copy(addr, drv->reg_data->seq, > + ARRAY_SIZE(drv->reg_data->seq) / 4); > + } > > /* > * ..and then the control registers. >