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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YSxe04GFzNwz5z3pryrGGbxCF4rljt4H X-Proofpoint-ORIG-GUID: YSxe04GFzNwz5z3pryrGGbxCF4rljt4H X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA2OCBTYWx0ZWRfX7ifYVO1VrwO9 2uaWKsyal7TYIgXXTDi76hHS/MDZcG5/kwWI8LvPyih8rS8SUwv2m9/RdrKv7CB+5QqlgJJu1tI kCBeRajqk3vMF041wqz+XxZjZImXndbDYYiJDjSaQjo4At/aOr3NVPliiLTrX5s7Tydf/3u+imt XjjlsOaL0mDzFHlzw0q8iogO4Ztdh/L7igK9STf4hMZpJzDzAgJmq3gasMwHEMuclRGDGi8Im7b VRPFb68lUDDuCJfXYrdVcy7C7CQ9JVzM88KRCjyk7ThV3sFwcrot+b2dwEnhKmTCzTbWyqWdXPD HG7AsZoMs5gTD+plgSe/1u4gW/gqnaq1v76zWo8wTNdLt0ghUYE8pBQvypHJlgdulzFJE8KoSYv 9op27r2X X-Authority-Analysis: v=2.4 cv=YMafyQGx c=1 sm=1 tr=0 ts=689d8e3d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=bSFmR1_Cq-7rNE1wWKgA:9 a=Kjs97tkqnXMi_ocT:21 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1011 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110068 On 8/14/2025 6:29 AM, Harrison Vanderbyl wrote: > Describe device tree entry for x1e80100 ufs device > Signed-off-by: Harrison Vanderbyl > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 91 ++++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index a9a7bb676c6f..effa776e3dd0 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2819,6 +2819,97 @@ tsens3: thermal-sensor@c274000 { > #thermal-sensor-cells = <1>; > }; > > + > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,x1e80100-ufshc", > + "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0 0x01d84000 0 0x3000>; > + > + > + interrupts = ; > + > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + > + lanes-per-direction = <2>; > + > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + > + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; > + reset-names = "rst"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + > + iommus = <&apps_smmu 0x1a0 0x0>; > + > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + > + freq-table-hz = <100000000 403000000>, > + <0 0>, > + <0 0>, > + <100000000 403000000>, > + <100000000 403000000>, > + <0 0>, > + <0 0>, > + <0 0>; > + Please use OPP table instead of freq-table-hz. > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; For Config Path, use QCOM_ICC_TAG_ACTIVE_ONLY. YOu can refer to ICC discussion link for SM8750 - https://lore.kernel.org/linux-devicetree/354f8710-a5ec-47b5-bcfa-bff75ac3ca71@oss.qualcomm.com/ > + interconnect-names = "ufs-ddr", "cpu-ufs"; > + > + qcom,ice = <&ice>; > + > + status = "disabled"; > + }; > + > + ufs_mem_phy: phy@1d80000 { > + compatible = "qcom,x1e80100-qmp-ufs-phy"; > + reg = <0 0x01d80000 0 0x2000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + > + clock-names = "ref", > + "ref_aux", > + "qref"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + ice: crypto@1d90000 { > + compatible = "qcom,x1e80100-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0 0x1d88000 0 0x8000>; > + > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + }; > + > usb_1_ss0_hsphy: phy@fd3000 { > compatible = "qcom,x1e80100-snps-eusb2-phy", > "qcom,sm8550-snps-eusb2-phy";