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Tue, 09 Jun 2026 06:24:34 -0700 (PDT) X-Received: by 2002:a05:6102:1487:b0:637:25ea:99c8 with SMTP id ada2fe7eead31-6fef3c04af3mr3212894137.1.1781011473857; Tue, 09 Jun 2026 06:24:33 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6912faea64dsm4883372a12.19.2026.06.09.06.24.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2026 06:24:33 -0700 (PDT) Message-ID: Date: Tue, 9 Jun 2026 15:24:30 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] dt-bindings: clock: qcom: Add bindings for PDM GP_MN clock divider To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=H+DrBeYi c=1 sm=1 tr=0 ts=6a281413 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=IMCAxTU7yX7nb3N5cp0A:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDEyNyBTYWx0ZWRfX04qXG6KuhBUS mmoyqvV/Y0U2ryS+J06gBTn8EWFfA1BEFqflQqVLGVFST9O1L0uCWKubw0C6E75gzdksS99N45G 8WNH5XVl4MqJki7oEG0S1aPRHIFTnwMI2iFlAeU1mj4FcedL2wOhkIAIhT5dc9bmF7sVjMkkETo exMjE1cgRw4fswN4UfPQFV2QevGbQ6ISsxdAE2/4mZLkXFKje/9m7UYEItgkAJEeGLe2ChnOzTb ZcEBlGtu1wCVKmVlKkTUS42z2I/HzY9dsA4GLmVuzBSoXGAm6Wf7mUNYv/YSwK6mN1/5S97HBl7 DoCm4a8zGRI25Slahm4Oisf4Z1kN0hyJ9MQ235Add5bhYMQksdDzYeH+l0zRyPmuvv56TebKCF6 keI1/Ry4sDMeXk/LC9hO6NsM+62yXZqB1KhWmzsQHzAb/LRE4RbbeC6H+MBi3nOFM9RSHIN+f+P NyIH4O3UiEAYlZn4nSw== X-Proofpoint-ORIG-GUID: -iTSF682i2HLr8Wka1idvUf6DMxE6Qni X-Proofpoint-GUID: -iTSF682i2HLr8Wka1idvUf6DMxE6Qni X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090127 On 6/2/26 5:21 PM, Taniya Das wrote: > Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN > clock divider. The hardware generates a fractional output frequency > from a fixed input clock (typically TCXO4) using the relation > Fout = Fin * (M / N), with duty cycle controlled by a separate D > register. The clock output is routed over a gpio controlled pin. > > Signed-off-by: Taniya Das > --- [...] > + #include > + gp_mn: clock-controller@88d3000 { > + compatible = "qcom,clk-gp-mnd"; The compatible must be SoC-specific, looking at the table, we could use these example socs for the versions of this block: 8960 (v1.0.0) 8974 (v1.1.1) 8994 (v2.1.0) 8996 (v2.2.0) > + reg = <0x88d3000 0xc>; Let's map the entire 0x4000 that this block spans Konrad