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([2a01:e0a:3d9:2080::fa42:7768]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd0dacd1sm42043981f8f.4.2026.01.13.00.11.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jan 2026 00:11:55 -0800 (PST) Message-ID: Date: Tue, 13 Jan 2026 09:11:54 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v6 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment To: Cristian Ciocaltea , Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org References: <20260113-phy-hdptx-frl-v6-0-8d5f97419c0b@collabora.com> <20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/13/26 00:20, Cristian Ciocaltea wrote: > Handle a bunch of reported checkpatch.pl complaints: > > CHECK: Alignment should match open parenthesis > > Signed-off-by: Cristian Ciocaltea > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > index 89710066d70c..3f8a7f4f5cd8 100644 > --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > @@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, > regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, > LN_TX_JEQ_EVEN_CTRL_RBR_MASK, > FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, > - ctrl->tx_jeq_even_ctrl)); > + ctrl->tx_jeq_even_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, > LN_TX_JEQ_ODD_CTRL_RBR_MASK, > FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, > - ctrl->tx_jeq_odd_ctrl)); > + ctrl->tx_jeq_odd_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, > LN_TX_SER_40BIT_EN_RBR_MASK, > FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); > @@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, > regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, > LN_TX_JEQ_EVEN_CTRL_HBR_MASK, > FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, > - ctrl->tx_jeq_even_ctrl)); > + ctrl->tx_jeq_even_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, > LN_TX_JEQ_ODD_CTRL_HBR_MASK, > FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, > - ctrl->tx_jeq_odd_ctrl)); > + ctrl->tx_jeq_odd_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, > LN_TX_SER_40BIT_EN_HBR_MASK, > FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); > @@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, > regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, > LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, > FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, > - ctrl->tx_jeq_even_ctrl)); > + ctrl->tx_jeq_even_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, > LN_TX_JEQ_ODD_CTRL_HBR2_MASK, > FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK, > - ctrl->tx_jeq_odd_ctrl)); > + ctrl->tx_jeq_odd_ctrl)); > regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, > LN_TX_SER_40BIT_EN_HBR2_MASK, > FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1)); > Reviewed-by: Neil Armstrong Thanks, Neil