From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD2A8C77B77 for ; Mon, 17 Apr 2023 04:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229756AbjDQEiF (ORCPT ); Mon, 17 Apr 2023 00:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230130AbjDQEhy (ORCPT ); Mon, 17 Apr 2023 00:37:54 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CC3A30E9; Sun, 16 Apr 2023 21:37:48 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33H4bSnx003038; Sun, 16 Apr 2023 23:37:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1681706249; bh=WGscPWkh913SexCumWOLYB7m18aSU2wZ99IzfLeUFzQ=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=wmJ9saEd/dh+Q4KzrXuoz79wRR0RTDbMLYqQys6Md+ciYNNy8AmIJE2sjUPRPAYqT NnlNFrnix/dD7eFiiIdd1qf909AVMdDDzXv2r3n/Xb+tgFoB2W1UcmIErOAFb8aWky m3h2XRb729asf/93OdrMSf8hiYkrfAlOY32X739Y= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33H4bSWR056664 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 16 Apr 2023 23:37:28 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Sun, 16 Apr 2023 23:37:28 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Sun, 16 Apr 2023 23:37:28 -0500 Received: from [172.24.145.182] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33H4bPaN018228; Sun, 16 Apr 2023 23:37:25 -0500 Message-ID: Date: Mon, 17 Apr 2023 10:07:24 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v2 1/5] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Content-Language: en-US To: Jayesh Choudhary , , CC: , , , , , , References: <20230414151553.339599-1-j-choudhary@ti.com> <20230414151553.339599-2-j-choudhary@ti.com> From: Vignesh Raghavendra In-Reply-To: <20230414151553.339599-2-j-choudhary@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jayesh On 14/04/23 20:45, Jayesh Choudhary wrote: > From: Siddharth Vadapalli > > The system controller node manages the CTRL_MMR0 region. > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. > > Signed-off-by: Siddharth Vadapalli > Signed-off-by: Jayesh Choudhary > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index e9169eb358c1..344f4ffa0b82 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -5,6 +5,9 @@ > * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include > +#include > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -26,6 +29,25 @@ l3cache-sram@200000 { > }; > }; > > + scm_conf: scm-conf@100000 { generic node name please: "syscon@" > + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; > + reg = <0x00 0x00100000 0x00 0x1c000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x00100000 0x1c000>; > + > + serdes_ln_ctrl: mux-controller@4080 { Either add reg property or replace @ with - Run make with W=12 to catch such errors. > + compatible = "mmio-mux"; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ > + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ > + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ > + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ > + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ > + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ > + }; > + }; > + > gic500: interrupt-controller@1800000 { > compatible = "arm,gic-v3"; > #address-cells = <2>; -- Regards Vignesh