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Fri, 30 Sep 2022 06:20:31 -0700 (PDT) Received: from [192.168.0.30] ([47.62.125.55]) by smtp.gmail.com with ESMTPSA id b3-20020adfee83000000b0022cc3e67fc5sm1987475wro.65.2022.09.30.06.20.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Sep 2022 06:20:30 -0700 (PDT) Message-ID: Date: Fri, 30 Sep 2022 15:20:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [PATCH v7, 1/3] mailbox: mtk-cmdq: add gce software ddr enable private data Content-Language: en-US To: Yongqiang Niu , CK Hu , Chun-Kuang Hu Cc: Jassi Brar , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Hsin-Yi Wang References: <20220930095915.13684-1-yongqiang.niu@mediatek.com> <20220930095915.13684-2-yongqiang.niu@mediatek.com> From: Matthias Brugger In-Reply-To: <20220930095915.13684-2-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/09/2022 11:59, Yongqiang Niu wrote: > if gce work control by software, we need set software enable > for MT8186 Soc > > there is a handshake flow between gce and ddr hardware, > if not set ddr enable flag of gce, ddr will fall into idle > mode, then gce instructions will not process done. > we need set this flag of gce to tell ddr when gce is idle or busy > controlled by software flow. > > Signed-off-by: Yongqiang Niu > --- > drivers/mailbox/mtk-cmdq-mailbox.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c > index 9465f9081515..04eb44d89119 100644 > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > @@ -38,6 +38,8 @@ > #define CMDQ_THR_PRIORITY 0x40 > > #define GCE_GCTL_VALUE 0x48 > +#define GCE_CTRL_BY_SW GENMASK(2, 0) > +#define GCE_DDR_EN GENMASK(18, 16) > > #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 > #define CMDQ_THR_ENABLED 0x1 > @@ -80,6 +82,7 @@ struct cmdq { > bool suspended; > u8 shift_pa; > bool control_by_sw; > + bool sw_ddr_en; > u32 gce_num; > }; > > @@ -87,6 +90,7 @@ struct gce_plat { > u32 thread_nr; > u8 shift; > bool control_by_sw; > + bool sw_ddr_en; > u32 gce_num; > }; > > @@ -129,7 +133,11 @@ static void cmdq_init(struct cmdq *cmdq) > > WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); > if (cmdq->control_by_sw) > - writel(0x7, cmdq->base + GCE_GCTL_VALUE); > + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); Thanks for doing this, but I think this should be part of a seperate patch. It's a cleanup and has nothing to do with the new sw_ddr_en, correct? Regards, Matthias > + > + if (cmdq->sw_ddr_en) > + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); > + > writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); > for (i = 0; i <= CMDQ_MAX_EVENT; i++) > writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); > @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev) > cmdq->thread_nr = plat_data->thread_nr; > cmdq->shift_pa = plat_data->shift; > cmdq->control_by_sw = plat_data->control_by_sw; > + cmdq->sw_ddr_en = plat_data->sw_ddr_en; > cmdq->gce_num = plat_data->gce_num; > cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); > err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,