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Fri, 3 Jan 2025 04:07:23 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 03 Jan 2025 09:07:03 +0000 From: "Jiaxun Yang" To: "Huacai Chen" Cc: "Xuerui Wang" , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: References: <20250102-la-misc-v1-1-8dc7db525e54@flygoat.com> Subject: Re: [PATCH] loongarch: time: Derive max_delta from prcfg1 tmrbits Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B41=E6=9C=883=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8A=E5= =8D=882:36=EF=BC=8CHuacai Chen=E5=86=99=E9=81=93=EF=BC=9A > Hi, Jiaxun, > > On Thu, Jan 2, 2025 at 10:05=E2=80=AFPM Jiaxun Yang wrote: >> >> As per arch spec, maximum timer bits is configurable and >> should not be hardcoded in any way. >> >> Use prcfg1 tmrbits to determine clockevent's max_delta >> to be conformance. >> >> Signed-off-by: Jiaxun Yang >> --- >> LA32R doesn't have prcfg, maybe we should handle this >> during cpu-probe and save it in cpuinfo_loongarch, >> >> What's your opinion, Huacai? >> --- >> arch/loongarch/include/asm/loongarch.h | 1 - >> arch/loongarch/kernel/time.c | 7 ++++++- >> 2 files changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/= include/asm/loongarch.h >> index 64ad277e096edd7d77af6f37e234d68e571764a4..a3cc4f8d4c4a0b0521ef2= b76c87fa57eca417d75 100644 >> --- a/arch/loongarch/include/asm/loongarch.h >> +++ b/arch/loongarch/include/asm/loongarch.h >> @@ -466,7 +466,6 @@ >> >> #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ >> #define CSR_TCFG_VAL_SHIFT 2 >> -#define CSR_TCFG_VAL_WIDTH 48 >> #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << = CSR_TCFG_VAL_SHIFT) >> #define CSR_TCFG_PERIOD_SHIFT 1 >> #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PE= RIOD_SHIFT) >> diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/tim= e.c >> index a07d7eff4dc5fb0f41f5fad02698ff7a84c7bc8a..bde2297f139c2d5e26894= a2ebc1748cc6fef3146 100644 >> --- a/arch/loongarch/kernel/time.c >> +++ b/arch/loongarch/kernel/time.c >> @@ -126,16 +126,21 @@ void sync_counter(void) >> >> int constant_clockevent_init(void) >> { >> + uint32_t tmrbits; > tmr is a strange short name, you can use timer_bits or tbits for short. That=E2=80=99s the one from the manual :-( I=E2=80=99d agree with you th= ough. > >> unsigned int cpu =3D smp_processor_id(); >> #ifdef CONFIG_PREEMPT_RT >> unsigned long min_delta =3D 100; >> #else >> unsigned long min_delta =3D 1000; >> #endif >> - unsigned long max_delta =3D (1UL << 48) - 1; >> + unsigned long max_delta; >> struct clock_event_device *cd; >> static int irq =3D 0, timer_irq_installed =3D 0; >> >> + tmrbits =3D read_csr_prcfg1() & CSR_CONF1_TMRBITS; >> + tmrbits =3D tmrbits >> CSR_CONF1_TMRBITS_SHIFT; >> + max_delta =3D CLOCKSOURCE_MASK(tmrbits + 1); > I prefer to evaluate the tbits and max_delta directly when declaring t= hem. Will do in v2. Thanks > > > Huacai >> + >> if (!timer_irq_installed) { >> irq =3D get_percpu_irq(INT_TI); >> if (irq < 0) >> >> --- >> base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 >> change-id: 20241223-la-misc-d610d14f947e >> >> Best regards, >> -- >> Jiaxun Yang >> --=20 - Jiaxun