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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id p17-20020a374211000000b007428e743508sm11708821qka.70.2023.03.22.10.41.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Mar 2023 10:41:46 -0700 (PDT) Message-ID: Date: Wed, 22 Mar 2023 18:41:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Reply-To: eric.auger@redhat.com Subject: Re: [PATCH v1 01/14] iommu: Add iommu_get_unmanaged_domain helper Content-Language: en-US To: Jason Gunthorpe Cc: Shameerali Kolothum Thodi , Nicolin Chen , "robin.murphy@arm.com" , "will@kernel.org" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "jean-philippe@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" References: <9b1077601cace998533129327f5e7ad946752d29.1678348754.git.nicolinc@nvidia.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jason, On 3/22/23 18:02, Jason Gunthorpe wrote: > On Wed, Mar 22, 2023 at 05:07:39PM +0100, Eric Auger wrote: > >>> It seems like Eric's issue is overly broad if we just want to block >>> RID reassignment that doesn't impact MMIO layout. >> IORT spec says >> >> " >> If reserved memory regions are present, the OS must preserve PCIe >> configuration performed by the boot >> firmware. This preservation is required to ensure functional continuity >> of the endpoints that are using the reserved >> memory regions. Therefore, RMR nodes must be supported by the inclusion >> of the PCI Firmware defined _DSM >> for ignoring PCI boot configuration, Function 5, in the ACPI device >> object of the PCIe host bridge in ACPI >> namespace. The _DSM method should return a value of 0 to indicate that >> the OS must honour the PCI >> configuration that the firmware has done at boot time. See [PCIFW] for >> more details on this _DSM method. >> " > I would say this spec language is overly broad. If the FW knows the > reserved memory regions it creates are not sensitive to PCI layout > then it should not be forced to set this flag. But do we have any guarantee the bus numbers can't change. I thought the guest was allowed to re-number at will? While further thinking at it, all RID ID mappings should be affected by this concern, I mean not only RID 2 RMRs? What do I miss? > >>> But, still, why do we care about this? >>> >>> The vIOMMU should virtualize the vSIDs right? So why does qemu give a >>> vSID list to the guest anyhow? Shouldn't the guest use an algorithmic >>> calculation from the vRID so that qemu can reverse it to the correct >>> vPCI device and thus the correct vfio_device and then dev id in the >>> iommu_domain? >> I don't understand how this changes the above picture? > We are forced to use RMR because of the hacky GIC ITS stuff. well we are not obliged to use RMRs. My first revisions did not use it and created a non direct S1 mapping. This is just a commodity that simplifies the integration and was nicely suggested by jean. > > ITS placement is not sensitive to PCI layout. > > ITS is not sensitive to bus numbers/etc. > > vSID to dev_id should also be taken care of by QEMU even if bus > numbers change and doesn't need to be fixed. agreed, hence the above question. > > So let's have a reason why we need to do all this weird stuff beyond > the spec says so. > > If there is no actual functional issue we should not restrict the > guest and provide RMR without the DSM method. Someone should go and > update the spec if this offends them :) > > Jason > Thanks Eric