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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e4e7ccbsm689895566b.59.2025.04.28.14.08.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 14:08:44 -0700 (PDT) Message-ID: Date: Mon, 28 Apr 2025 23:08:42 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 To: Johan Hovold , Konrad Dybcio Cc: Wenbin Yao , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com References: <20250425092955.4099677-1-quic_wenbyao@quicinc.com> <20250425092955.4099677-3-quic_wenbyao@quicinc.com> <4bb58766-a080-4351-87f5-79a98219171c@oss.qualcomm.com> <306ce1fa-be83-4f13-bedd-97a20448d162@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: cpGMY79SFRBkp3L57uESk24pHQZQ6qBr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDE3MCBTYWx0ZWRfX/tdSRZTbY9dg pZ0ErMKXgSIhVa2U7NPf2RdRg/rZ86lLXWXg2LPOprT6wVPb66FzpRrGLlfHlMJZfEthQq3qja8 StW5LiEQ16UbdfDgzQ8e/6TVjccKNyEYG75mVf5NiHRf0RFaKXa6vAr6e4om0fm/hCf04NYrrvF yWa7UYXo/uufkgk6UDagciqMChdjxQPqVNWpYWXOdYqbwUt3lGgfsPHv6XSn9spvZcyTULyhDM5 WcCvAOcQBOqUZtjKIUv7S8jxp4vTCHYDWEvXBtJISTuLia4aSiu6Jg28Aj/0Gs2h57lw78k9ppt 3ZbpnxFX7Wds2chVAMhQ7GX+2WAHzEXBp4UbKeQNcmMKETZ9ccP4a+WQN5L3XHbkM8vTk3JGiJW LxAMuo2wYqucQob3GhJ72rCs7zhWDW38kpc0IO6uSMPm10u11cgYEF81X+2eLBBGYjn4YFlB X-Proofpoint-GUID: cpGMY79SFRBkp3L57uESk24pHQZQ6qBr X-Authority-Analysis: v=2.4 cv=DKWP4zNb c=1 sm=1 tr=0 ts=680fee5e cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=jsbeokMXWjskDHubqLoA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280170 On 4/28/25 1:16 PM, Johan Hovold wrote: > On Sat, Apr 26, 2025 at 12:44:57PM +0200, Konrad Dybcio wrote: >> On 4/25/25 1:55 PM, Johan Hovold wrote: >>> On Fri, Apr 25, 2025 at 12:22:56PM +0200, Konrad Dybcio wrote: >>>> On 4/25/25 11:29 AM, Wenbin Yao wrote: >>>>> From: Qiang Yu >>>>> >>>>> Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot >>>>> voltage rails can be described under this node in the board's dts. >>>>> >>>>> Signed-off-by: Qiang Yu >>>>> Signed-off-by: Wenbin Yao >>>>> --- >>>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ >>>>> 1 file changed, 11 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>>> index 46b79fce9..430f9d567 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>>> @@ -3287,6 +3287,17 @@ opp-128000000 { >>>>> opp-peak-kBps = <15753000 1>; >>>>> }; >>>>> }; >>>>> + >>>>> + pcie3port: pcie@0 { >>>> >>>> @0,0 for PCIe adressing (bus,device) >>> >>> No, the bus number is not included in the unit address, so just the >>> device number (0) is correct here (when the function is 0) IIUC. >> >> Some DTs definitely have that, but I couldn't find any documentation to >> back the syntax up or explain it properly > > It's part of the spec: > > http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf > > The first number is the device number and the second is the function > which can be left out if zero. OK thank you for clarifying Konrad