From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A3191EFF9F; Mon, 23 Jun 2025 07:26:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663619; cv=none; b=DMRVhi+rJjr7OX5rhxKlO+JVF7QHhtKQBGBJaze7pFe+jsy/fBPHu7SdZ11OMn+CqLrtG/Fm8Ha/Zz3mYmZ+Xa+R035o7AMQYngyTtpc6ShXyuQPOkFYpcN1rQDjT71sVYFacfwElyVcX8HxHwzIID1DHMs+0u5P/LcQTe3LYKY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663619; c=relaxed/simple; bh=PrmiFlnUXWUSiWNTv2xaiY/o4S3vaZe/dqM1S2sZKv4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lGu9D0EGYsAil+iRZf95d6/bIQe7B1ioSQTWiH2MsAHr5VFC+ndhedqPAM3X0EgoqE986QkZWuMsAoGqf++mfPpFxN+b4vBLPrXJI9mHtgecCQhDoRyyIqZ0t25JO8sgp0jPzyFl18+489fYHgtrhmHs/c31Xoo+g+Bi+gZuPcE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=RM91PLVd; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="RM91PLVd" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=j5uT5DWaYtpQ2U6usaprpgbgjh4e7uOTUA89hl1Rr7I=; b=RM91PLVd+vFdJAn3Amhhq9fLnp 78a0HZ43BM06fd7yO6f7errbSVBB/F89x+pLm80wcJJ7vAcTafJfay8RxIN8snu5DaYDpXQp/yveI 33pQFPD9vdU2NyT8x/9cUNgGI0JffYC76/fMqIz88BHR9qFKF7VJTIPNgxWNTz770UPA=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1uTbZj-00GfK8-Gc; Mon, 23 Jun 2025 09:26:43 +0200 Date: Mon, 23 Jun 2025 09:26:43 +0200 From: Andrew Lunn To: Inochi Amaoto Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , Alexander Sverdlin , Thomas Bonnefille , Yu Yuan , Ze Huang , netdev@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: Re: [PATCH net-next RFC v2 4/4] riscv: dts: sophgo: Add ethernet configuration for Huashan Pi Message-ID: References: <20250623003049.574821-1-inochiama@gmail.com> <20250623003049.574821-5-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250623003049.574821-5-inochiama@gmail.com> On Mon, Jun 23, 2025 at 08:30:46AM +0800, Inochi Amaoto wrote: > Add configuration for ethernet controller on Huashan Pi. > > Signed-off-by: Inochi Amaoto > --- > arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts > index 26b57e15adc1..86f76159c304 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts > +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts > @@ -55,6 +55,16 @@ &emmc { > non-removable; > }; > > +&gmac0 { > + status = "okay"; > + phy-handle = <&internal_ephy>; > + phy-mode = "internal"; > +}; Since the PHY is internal, it should be part of the SoC .dtsi file, same as any other peripheral. The board .dts file can then enable it. Andrew --- pw-bot: cr