Hi,

Le jeudi 06 novembre 2025 à 14:13 +0800, Kyrie Wu a écrit :
> The dram addr of vp9 decoder tile number, which use dram mode
> to set tile information, may reach to 36bits for 4096x2176.
> It needs to get the highest 4bit of tile buffer address to
> set tile buffer address.

An after thought, I don't see any call to vb2_dma_contig_set_max_seg_size() or
dma_set_coherent_mask() with DMA_BIT_MASK(32)/DMA_BIT_MASK(36) in this driver.
How do you control this ?

Nicolas

> 
> Fixes: 5d418351ca8f1 ("media: mediatek: vcodec: support stateless VP9
> decoding")
> 
> Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com>
> ---
>  .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c       | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git
> a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
> b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
> index d966914db4b9..91c563c049bd 100644
> ---
> a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
> +++
> b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
> @@ -1156,7 +1156,10 @@ static int vdec_vp9_slice_setup_tile_buffer(struct
> vdec_vp9_slice_instance *inst
>  			tiles->size[i][j] = size;
>  			if (tiles->mi_rows[i]) {
>  				*tb++ = (size << 3) + ((offset << 3) & 0x7f);
> -				*tb++ = pa & ~0xf;
> +				*tb = pa & ~0xf;
> +				if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
> +					*tb |= (pa >> 32) & 0xf;
> +				tb++;
>  				*tb++ = (pa << 3) & 0x7f;
>  				mi_row = (tiles->mi_rows[i] - 1) & 0x1ff;
>  				mi_col = (tiles->mi_cols[j] - 1) & 0x3f;