From: Jon Hunter <jonathanh@nvidia.com>
To: Akhil R <akhilrajeev@nvidia.com>
Cc: <dan.j.williams@intel.com>, <dmaengine@vger.kernel.org>,
<kyarlagadda@nvidia.com>, <ldewangan@nvidia.com>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<p.zabel@pengutronix.de>, <rgumasta@nvidia.com>,
<thierry.reding@gmail.com>, <vkoul@kernel.org>,
Pavan Kunapuli <pkunapuli@nvidia.com>
Subject: Re: [PATCH v8 2/4] dmaengine: tegra: Add tegra gpcdma driver
Date: Tue, 5 Oct 2021 08:50:52 +0100 [thread overview]
Message-ID: <bd2fa473-7285-f905-ecec-5e97a177d918@nvidia.com> (raw)
In-Reply-To: <1632759090-7965-3-git-send-email-akhilrajeev@nvidia.com>
On 27/09/2021 17:11, Akhil R wrote:
> Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
> supports dma transfers between memory to memory, IO peripheral to memory
> and memory to IO peripheral.
>
> Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
> Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/tegra186-gpc-dma.c | 1298 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1311 insertions(+)
> create mode 100644 drivers/dma/tegra186-gpc-dma.c
...
> +static int tegra_dma_terminate_all(struct dma_chan *dc)
> +{
> + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
> + unsigned long wcount = 0;
> + unsigned long status;
> + unsigned long flags;
> + int err;
> +
> + raw_spin_lock_irqsave(&tdc->lock, flags);
> +
> + if (!tdc->dma_desc) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return 0;
> + }
> +
> + if (!tdc->busy)
> + goto skip_dma_stop;
> +
> + if (tdc->tdma->chip_data->hw_support_pause)
> + err = tegra_dma_pause(tdc);
> + else
> + err = tegra_dma_stop_client(tdc);
> +
> + if (err) {
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return err;
> + }
> +
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
> + dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
> + tegra_dma_xfer_complete(tdc);
> + status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
> + }
> +
> + wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
> + tegra_dma_stop(tdc);
> +
> + if (tdc->dma_desc)
This is always true here right?
> + tdc->dma_desc->bytes_transferred +=
> + tdc->dma_desc->bytes_requested - (wcount * 4);
> +
> +skip_dma_stop:
> + tegra_dma_sid_free(tdc);
> + kfree(tdc->dma_desc);
> + vchan_free_chan_resources(&tdc->vc);
> +
> + raw_spin_unlock_irqrestore(&tdc->lock, flags);
> + return 0;
> +}
...
> +static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
> + u32 burst_size, enum dma_slave_buswidth slave_bw,
> + int len)
There are a few places like this where the alignment could be fixed.
...
> +static struct dma_async_tx_descriptor *
> +tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
> + dma_addr_t src, size_t len, unsigned long flags)
> +{
Spacing here.
> +static struct dma_async_tx_descriptor *
> +tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
> + unsigned int sg_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{
Alignment here.
Jon
--
nvpublic
next prev parent reply other threads:[~2021-10-05 7:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 16:11 [PATCH v8 0/4] Add Nvidia Tegra GPC-DMA driver Akhil R
2021-09-27 16:11 ` [PATCH v8 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-09-27 16:11 ` [PATCH v8 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2021-10-05 7:50 ` Jon Hunter [this message]
2021-09-27 16:11 ` [PATCH v8 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-09-27 16:11 ` [PATCH v8 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
2021-10-05 7:43 ` [PATCH v8 0/4] Add Nvidia Tegra GPC-DMA driver Jon Hunter
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