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Thu, 22 Oct 2026 14:59:16 -0700 (PDT) Received: from [192.168.1.13] ([106.222.228.226]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-369d9d89b14sm685365eec.14.2026.10.22.14.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 14:59:15 -0700 (PDT) Message-ID: Date: Fri, 23 Oct 2026 03:29:08 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] drm/msm/a5xx: Reset the GPU when resuming it To: fabricioakio@gmail.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Paul Sajna , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter References: <20261019-a5xx-gpu-pm-v2-0-457aafbb28da@gmail.com> <20261019-a5xx-gpu-pm-v2-1-457aafbb28da@gmail.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20261019-a5xx-gpu-pm-v2-1-457aafbb28da@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: lYm5dEW7PQ4cJs0k8XiqdTkHTyQnpdlt X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfX95cIzQg4Uss2 8uXnGCC9h2TISliX4NnG9u/lLqAjRng3thbUm/bftTWVihaZdj+U4g/8/ecr7hskOlCxZEuWA+z vKyHCO/wSwbvpee+/Yxo2nktoXF3JcY= X-Authority-Analysis: v=2.4 cv=VNZIDNPX c=1 sm=1 tr=0 ts=6ada8736 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ipsIN8yD8anPosRfiFfp5w==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=Gbw9aFdXAAAA:8 a=pGLkceISAAAA:8 a=aq2bxKA37D_GVACvEnsA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=9vIz8raoGPyDa4jBFAYH:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDA4NyBTYWx0ZWRfXwYrzhxw+ASxY yLOzc8UqqcrliJRD3ooyGGZGiKku3MXOmRTG8HCxTXtGXhGwj/ic1LxiGtegaS+n/mz40lGEqHO T5geB0kttBTYi+eEKqD+Qq85VOkQva0hgq1OMa7+vKACCqUSLf5aOYrMaE4kdbJsvGJNNENUXba jlhfcSdkORN/OCfUhMKgeZdXnogMDU/ZTiFsQH7c6cXhkvBZV2I0GFbAE4oDNakRQFl1AGivYsu aEAiKX8S7oTRVj8lt68TZxKeI6/qSDmJNF6NWTn6bHMvKkuGDzsvqOxuMDvcNm9Wb/iKmISA8Ms xnUAIBIQv/6zEKugF/d0eReaGHwls2u2O2aHW5f51z9oGEcYi/z1cfTCUT5tjtWTjJ8/v5br3E3 5Sl0/GDyW5FPggk6/EUzb8ffDA4tbArbctX4at52S72ePw3Ad9xHw54y7G4/eCSUw3rFqRzVvpt bFkdsT51Klw0fzoZHyA== X-Proofpoint-ORIG-GUID: lYm5dEW7PQ4cJs0k8XiqdTkHTyQnpdlt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-22_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220087 On 10/20/2026 7:35 AM, Fabricio Akio via B4 Relay wrote: > From: Fabricio Akio > > On SDM630, SDM660 and MSM8998 the GPU's GX power domain belongs to its > SMMU, not to the GPU, so GX switches off only once the SMMU suspends as This is incorrect. There is no Adreno GPU where SMMU is powered by GX. I looked at the DT of SDM630 and I don't understand it. Seems like a creative workaround to vote different power domains. Please reword GX -> CX here. Adreno SMMU is powered by CX GDSC in every chipset. In some chipsets, the core GPU blocks are also powered via CX GDSC. So it makes sense to do a SW RESET in case CX didn't collapse due to a vote from the SMMU driver or something. > well. A GPU resumed with GX still on keeps its state, and the CP keeps > its ringbuffer read pointer. a5xx_hw_init() then rewinds the ringbuffer > and writes CP_ME_INIT at its start, while the CP goes on from its old > position, executes stale ringbuffer contents and hangs: > > timeout waiting to drain ringbuffer 0 rptr/wptr = 23/C > > Soft reset the GPU in a5xx_pm_resume() once it is powered, so that > every resume starts from the reset state. The downstream driver resets > only when it finds the GPU's power left on; resetting a GPU that was > powered off changes nothing, and on A508 the reset takes about 2 us of > a resume of about 1.5 ms, so do it every time. > > The reset also clears the busy counter, which msm_gpu_pm_resume() has > just sampled as devfreq's baseline. Take the baseline again after the > reset, or the next devfreq poll subtracts the old count from the new > one, wraps, and sets the GPU to its top frequency. > > Signed-off-by: Fabricio Akio > --- > Changes in v2: > - Take devfreq's busy-cycle baseline again after the reset, which > clears the busy counter (Sashiko) > > Tested on A508 only; the reset runs on every A5xx. > > A stall with the same signature, the CP's read pointer past the write > pointer just after CP_ME_INIT, was reported on an A509: > https://lore.kernel.org/linux-arm-msm/20260308-adreno-ringbuffer-drain-timeout-recovery-v1-1-985a33faf108@postmarketos.org/ > This may be the root cause of the A509 stall Paul Sajna reported there. > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 15 +++++++++++++++ > drivers/gpu/drm/msm/msm_gpu.h | 1 + > drivers/gpu/drm/msm/msm_gpu_devfreq.c | 17 +++++++++++++++++ > 3 files changed, 33 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 16c7335c4b1f..0aff8252a00f 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -1367,6 +1367,21 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) > if (ret) > return ret; > > + /* > + * The GX power domain is not necessarily switched off while we are > + * suspended: on SDM630, SDM660 and MSM8998 it follows the GPU's SMMU > + * rather than the GPU. If it stayed on, the CP still holds its old > + * ringbuffer read pointer and would execute stale ringbuffer contents > + * once hw_init restarts it. Soft reset the GPU so that it always > + * resumes from its reset state. > + */ > + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); > + gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); > + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); > + > + /* The reset cleared the busy counter devfreq has just sampled */ > + msm_devfreq_resample_busy(gpu); Instead of a new API, we can just move msm_devfreq_resume() here. That will align with the A6xx sequence. -Akhil. > + > /* Adreno 505, 506, 508, 509, 510, 512 needs manual RBBM sus/res control */ > if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) { > /* Halt the sp_input_clk at HM level */ > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index d27d54bdb7a7..0e0768c15bcc 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -735,6 +735,7 @@ static inline struct msm_context *msm_context_get( > void msm_devfreq_init(struct msm_gpu *gpu); > void msm_devfreq_cleanup(struct msm_gpu *gpu); > void msm_devfreq_resume(struct msm_gpu *gpu); > +void msm_devfreq_resample_busy(struct msm_gpu *gpu); > void msm_devfreq_suspend(struct msm_gpu *gpu); > void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor); > void msm_devfreq_active(struct msm_gpu *gpu); > diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > index 2e1d5c343272..2e963bff3f61 100644 > --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c > +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > @@ -242,6 +242,23 @@ void msm_devfreq_resume(struct msm_gpu *gpu) > devfreq_resume_device(df->devfreq); > } > > +/* > + * Take a new busy cycles baseline, for a GPU that resets its busy counter > + * after msm_devfreq_resume() has sampled it. > + */ > +void msm_devfreq_resample_busy(struct msm_gpu *gpu) > +{ > + struct msm_gpu_devfreq *df = &gpu->devfreq; > + unsigned long sample_rate; > + > + if (!has_devfreq(gpu)) > + return; > + > + mutex_lock(&df->lock); > + df->busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); > + mutex_unlock(&df->lock); > +} > + > void msm_devfreq_suspend(struct msm_gpu *gpu) > { > struct msm_gpu_devfreq *df = &gpu->devfreq; >