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Date: Thu, 4 Feb 2010 01:22:19 +0100
Message-ID: <bd4cb8901002031622q42e3dba3y76168a71cfb75165@mail.gmail.com>
Subject: Re: [RFC][PATCH] perf_events, x86: PEBS support
From: Stephane Eranian <eranian@google.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@elte.hu>, Paul Mackerras <paulus@samba.org>,
       "Metzger, Markus T" <markus.t.metzger@intel.com>,
       lkml <linux-kernel@vger.kernel.org>,
       Robert Richter <robert.richter@amd.com>,
       "David S. Miller" <davem@davemloft.net>,
       Jamie Iles <jamie.iles@picochip.com>, Paul Mundt <lethal@linux-sh.org>,
       Arjan van de Ven <arjan@infradead.org>,
       "H. Peter Anvin" <hpa@zytor.com>, perfmon2-devel@lists.sf.net
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On Thu, Feb 4, 2010 at 1:03 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Thu, 2010-02-04 at 00:51 +0100, Stephane Eranian wrote:
>> On Thu, Feb 4, 2010 at 12:50 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>> > On Wed, 2010-02-03 at 15:40 +0100, Peter Zijlstra wrote:
>> >>
>> >> If only they would reset the counter on overflow instead of on record,
>> >> that would solve quite a few issues I imagine.
>> >
>> > So I tried enabling the regular PMC overflow interrupt and reprogramming
>> > the counter from that, but touching the counter seems to destroy the
>> > PEBS assist, so much for that idea.
>> >
>> Yes, you have to leave the INT bit off, otherwise you get an
>> interrupt for each overflow, thus you lose the buffer advantage.
>
> Well sure, but that's not the point. I was thinking that if we need to
> do single event pebs anyway, we might as well try to reprogram on the
> PMC overflow interrupt instead of on the PEBS overflow and curb some of
> that drift.
>
With INT on, you get the interrupt on the first overflow and incur the
regular skid. There is nothing you can do to make PEBS better from
SW. The HW has to improve. I have reported those issues to Intel
a long time ago. They understand them quite well and I am hopeful
things will improve over time.