From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48C201EE00A for ; Wed, 25 Mar 2026 19:20:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774466416; cv=none; b=IyI+OX2Zf/dV3Ny4aEKGlPXnSzR9KYiivWxtj+XN7lTTpeadlCq226cRd7uRdigFfn4DqAFYzeEInUbvQj4K2IwN6RzIzVAYEZjSabm0MzDEpRrzRlarkUsyN3eHvrxQpPpmUdVPTtgS93KDrNocUe/z50jI2NatEII3DjlL/Yo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774466416; c=relaxed/simple; bh=hcrk0gPTl09RsQ8K62XAnKbAFcxKavDbBTD8wb9BT0Q=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=ZqMUzCcmWz/aEeIRVJ9eb5cGSGmLpgCt3Vd9mOzQLMpgvllPQcQ+hgmxaufHpVCHJ2YajImjmiIowseNwV2tafI+XAEqJyHB/354gBWibp33JRgwGkY2pUJSM1ML+fLxE+RmXPVQoNSJdhIFjXjcLXeZfHC2q5u2LiN7CVW73Wk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=gcXJze57; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="gcXJze57" Received: from dog.kanata.rendec.net (pool-174-112-193-187.cpe.net.cable.rogers.com [174.112.193.187]) by mail.mindbit.ro (Postfix) with ESMTPSA id 9AFDDC24B6; Wed, 25 Mar 2026 21:20:03 +0200 (EET) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro 9AFDDC24B6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1774466404; bh=rZwcLwgy7b4X57Ew8mG2hs+Smd/G2bKloIX3lMhPre0=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=gcXJze5758X9ZEOdR0A6bpB7yjJXizCDXCPxizEfrEbtKJEPYqvcVV6V/VBKzj24P sAnqy0mTXRhHYU6OdjsNYNPuAdcPibT1nLnl/PAGrZg1crQFXAZT2VOWUyp9xj7ZsG dYEHzKczArPEzPc5ee7kDyYP3a0thQHeMzw6bsbuYSfkUhJjP5LG16mjtJn6265mPo ya6xt6qiOdgug2I8fSvpv4bhDAS9M2esdfKfO8cQLhOqpi0NJZr1mvJFlFYQ3HxhOS tfLG7t2YY4By885loTmGhdAmlkUwpfif78FcLhtwzHUy5JtVK/KlY9nwQWAvpa0+ch TrJ/LEqkmM6Yg== Message-ID: Subject: Re: [patch v2 04/14] x86/irq: Make irqstats array based From: Radu Rendec To: Thomas Gleixner , LKML Cc: x86@kernel.org, Dmitry Ilvokhin , Neil Horman , Florian Fainelli Date: Wed, 25 Mar 2026 15:20:01 -0400 In-Reply-To: References: <20260320131108.344376329@kernel.org> <20260320132102.297759330@kernel.org> <874im5gfzp.ffs@tglx> <871ph9ges3.ffs@tglx> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-03-24 at 16:32 -0400, Radu Rendec wrote: > On Tue, 2026-03-24 at 21:21 +0100, Thomas Gleixner wrote: > > On Tue, Mar 24 2026 at 20:54, Thomas Gleixner wrote: > >=20 > > > On Mon, Mar 23 2026 at 15:24, Radu Rendec wrote: > > > > On Fri, 2026-03-20 at 14:21 +0100, Thomas Gleixner wrote: > > > > > =C2=A0arch/x86/include/asm/hardirq.h=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0=C2=A0 69 +++++----- > > > >=20 > > > > I believe this breaks scripts/gdb/linux/interrupts.py, particularly= the > > > > x86_show_irqstat() function, which still expects individual members= in > > > > struct irq_cpustat_t. > > >=20 > > > Uurg. I did not even know this exists. Let me try to polish the snake= . > >=20 > > Something like the below should work, now I have to figure out how to > > test it. >=20 > At a glance, it looks about right (although I haven't tested it). The > test procedure involves running the kernel in a Qemu VM and attaching > with gdb to Qemu's gdb server (apologies if I'm just stating the > obvious here). It's briefly described here: > Documentation/dev-tools/gdb-kernel-debugging.rst >=20 > The documentation doesn't elaborate on Qemu parameters. I'm using > something like this: >=20 > qemu-system-x86_64 -nographic -m 1G -accel kvm -machine q35,hpet=3Doff -c= pu host -smp 4 \ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 -netdev bridge,br=3Dvbr-nat,id= =3Dnet0 -device virtio-net-pci,mac=3D52:54:98:aa:bb:cc,netdev=3Dnet0 \ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 -drive file=3Droot.img,format= =3Draw,if=3Dvirtio \ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 -kernel bzImage \ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 -append "console=3DttyS0 root= =3D/dev/vda1 rw nokaslr" \ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 -s >=20 > Happy to help if something doesn't quite work for you. >=20 > > ---- > > --- a/scripts/gdb/linux/interrupts.py > > +++ b/scripts/gdb/linux/interrupts.py > > @@ -97,8 +97,8 @@ irq_desc_type =3D utils.CachedType("struct > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%*s: %10u\n= " % (prec, "ERR", cnt['counter']) > > =C2=A0=C2=A0=C2=A0=C2=A0 return text > > =C2=A0 > > -def x86_show_irqstat(prec, pfx, field, desc): > > -=C2=A0=C2=A0=C2=A0 irq_stat =3D gdb.parse_and_eval("&irq_stat") > > +def x86_show_irqstat(prec, pfx, idx, desc): > > +=C2=A0=C2=A0=C2=A0 irq_stat =3D gdb.parse_and_eval("&irq_stat.counts[I= RQ_COUNT_%s]" %idx) > > =C2=A0=C2=A0=C2=A0=C2=A0 text =3D "%*s: " % (prec, pfx) > > =C2=A0=C2=A0=C2=A0=C2=A0 for cpu in cpus.each_online_cpu(): > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 stat =3D cpus.per_cpu(= irq_stat, cpu) > > @@ -118,32 +118,51 @@ irq_desc_type =3D utils.CachedType("struct > > =C2=A0=C2=A0=C2=A0=C2=A0 text =3D x86_show_irqstat(prec, "NMI", '__nmi_= count', 'Non-maskable interrupts') > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_LOCAL_APIC: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "LOC", 'apic_timer_irqs', "Local timer interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "SPU", 'irq_spurious_count', "Spurious interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PMI", 'apic_perf_irqs', "Performance monitoring interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "IWI", 'apic_irq_work_irqs', "IRQ work interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "RTR", 'icr_read_retry_count', "APIC ICR read retries") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "LOC", 'APIC_TIMER', "Local timer interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "SPU", 'SPURIOUS', "Spurious interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PMI", 'APIC_PERF', "Performance monitoring interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "IWI", 'IRQ_WORK', "IRQ work interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "RTR", 'ICR_READ_RETRY', "APIC ICR read retries") > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if utils.gdb_eval_or_n= one("x86_platform_ipi_callback") is not None: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tex= t +=3D x86_show_irqstat(prec, "PLT", 'x86_platform_ipis', "Platform interru= pts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tex= t +=3D x86_show_irqstat(prec, "PLT", 'X86_PLATFORM_IPI', "Platform interrup= ts") > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_SMP: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "RES", 'irq_resched_count', "Rescheduling interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "CAL", 'irq_call_count', "Function call interrupts") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "TLB", 'irq_tlb_count', "TLB shootdowns") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "RES", 'RESCHEDULE', "Rescheduling interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "CAL", 'CALL_FUNCTION', "Function call interrupts") > > + > > +=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(prec, "TLB", 'TLB', "TLB= shootdowns") > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_THERMAL_VECTOR: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "TRM", 'irq_thermal_count', "Thermal events interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "TRM", 'THERMAL_APIC', "Thermal events interrupts") > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE_THRESHOLD: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "THR", 'irq_threshold_count', "Threshold APIC interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "THR", 'THRESHOLD_APIC', "Threshold APIC interrupts") > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE_AMD: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "DFR", 'irq_deferred_error_count', "Deferred Error APIC interrupts") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "DFR", 'DEFERRED_ERROR', "Deferred Error APIC interrupts") > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_mce= (prec, "&mce_exception_count", "MCE", "Machine check exceptions") > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_mce= (prec, "&mce_poll_count", "MCP", "Machine check polls") > > =C2=A0 > > +=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_HV_CALLBACK_VECTOR: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, 'HYP', 'HYPERVISOR_CALLBACK', 'Hypervisor callback interrupts') > > + > > +=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_HYPERV: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, 'HRE', 'HYPERV_REENLIGHTENMENT', 'Hyper-V reenlightenment interrupts'= ) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, 'HVS', 'HYPERV_STIMER0', 'Hyper-V stimer0 interrupts') > > + > > +=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_KVM: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PIN", 'POSTED_INTR', 'Posted-interrupt notification event') > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "NPI", 'POSTED_INTR_NESTED', 'Nested posted-interrupt event') > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PIW", 'POSTED_INTR_WAKEUP', 'Posted-interrupt wakeup event') > > + > > +=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_GUEST_PERF_EVENTS: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "VPMI", 'PERF_GUEST_MEDIATED_PMI', 'Perf Guest Mediated PMI') > > + > > +=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_POSTED_MSI: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PIN", 'POSTED_MSI_NOTIFICATION', 'Posted MSI notification event') > > + > > =C2=A0=C2=A0=C2=A0=C2=A0 text +=3D show_irq_err_count(prec) > > =C2=A0 > > =C2=A0=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_IO_APIC: > > @@ -151,11 +170,6 @@ irq_desc_type =3D utils.CachedType("struct > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if cnt is not None: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 text +=3D "%*s: %10u\n" % (prec, "MIS", cnt['counter']) > > =C2=A0 > > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_KVM: > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PIN", 'kvm_posted_intr_ipis', 'Posted-interrupt notification event') > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "NPI", 'kvm_posted_intr_nested_ipis', 'Nested posted-interrupt event'= ) > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(= prec, "PIW", 'kvm_posted_intr_wakeup_ipis', 'Posted-interrupt wakeup event'= ) > > - > > =C2=A0=C2=A0=C2=A0=C2=A0 return text > > =C2=A0 > > =C2=A0def arm_common_show_interrupts(prec): I tested it, and it's very close but requires a few extra changes, which I included as a patch at the bottom. There's one more gotcha: in the next patch (patch 5) you rename nr_irqs to total_nr_irqs, and the change must be applied to interrupts.py as well. It's used at the beginning of the LxInterruptList.invoke() function. One other issue I came across is that the fields below are not defined for me (even though the corresponding config options do exist in the kernel config file): constants.LX_CONFIG_X86_HV_CALLBACK_VECTOR constants.LX_CONFIG_HYPERV constants.LX_CONFIG_GUEST_PERF_EVENTS constants.LX_CONFIG_X86_POSTED_MSI I didn't spend the time to figure out why. I'm pretty sure this is completely unrelated to your changes. --- a/scripts/gdb/linux/interrupts.py +++ b/scripts/gdb/linux/interrupts.py @@ -102,20 +102,12 @@ def x86_show_irqstat(prec, pfx, idx, desc): text =3D "%*s: " % (prec, pfx) for cpu in cpus.each_online_cpu(): stat =3D cpus.per_cpu(irq_stat, cpu) - text +=3D "%10u " % (stat[field]) - text +=3D " %s\n" % (desc) - return text - -def x86_show_mce(prec, var, pfx, desc): - pvar =3D gdb.parse_and_eval(var) - text =3D "%*s: " % (prec, pfx) - for cpu in cpus.each_online_cpu(): - text +=3D "%10u " % (cpus.per_cpu(pvar, cpu).dereference()) + text +=3D "%10u " % (stat.dereference()) text +=3D " %s\n" % (desc) return text =20 def x86_show_interupts(prec): - text =3D x86_show_irqstat(prec, "NMI", '__nmi_count', 'Non-maskable in= terrupts') + text =3D x86_show_irqstat(prec, "NMI", 'NMI', 'Non-maskable interrupts= ') =20 if constants.LX_CONFIG_X86_LOCAL_APIC: text +=3D x86_show_irqstat(prec, "LOC", 'APIC_TIMER', "Local timer= interrupts") @@ -142,8 +134,8 @@ def x86_show_interupts(prec): text +=3D x86_show_irqstat(prec, "DFR", 'DEFERRED_ERROR', "Deferre= d Error APIC interrupts") =20 if constants.LX_CONFIG_X86_MCE: - text +=3D x86_show_mce(prec, "&mce_exception_count", "MCE", "Machi= ne check exceptions") - text +=3D x86_show_mce(prec, "&mce_poll_count", "MCP", "Machine ch= eck polls") + text +=3D x86_show_irqstat(prec, "MCE", "MCE_EXCEPTION", "Machine = check exceptions") + text +=3D x86_show_irqstat(prec, "MCP", "MCE_POLL", "Machine check= polls") =20 if constants.LX_CONFIG_X86_HV_CALLBACK_VECTOR: text +=3D x86_show_irqstat(prec, 'HYP', 'HYPERVISOR_CALLBACK', 'Hy= pervisor callback interrupts')