From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D2FC433C1 for ; Tue, 23 Mar 2021 17:06:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA8DE619B8 for ; Tue, 23 Mar 2021 17:06:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbhCWRFd (ORCPT ); Tue, 23 Mar 2021 13:05:33 -0400 Received: from foss.arm.com ([217.140.110.172]:49324 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229669AbhCWRF3 (ORCPT ); Tue, 23 Mar 2021 13:05:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 809361042; Tue, 23 Mar 2021 10:05:29 -0700 (PDT) Received: from [10.57.55.187] (unknown [10.57.55.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B24123F718; Tue, 23 Mar 2021 10:05:27 -0700 (PDT) Subject: Re: (subset) [PATCH v5 00/19] coresight: Add support for ETE and TRBE To: Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: leo.yan@linaro.org, catalin.marinas@arm.com, Linu Cherian , Will Deacon , coresight@lists.linaro.org, Peter Zilstra , anshuman.khandual@arm.com, mike.leach@linaro.org, mathieu.poirier@linaro.org, linux-kernel@vger.kernel.org References: <20210323120647.454211-1-suzuki.poulose@arm.com> <161651726490.2050093.5536833570808361940.b4-ty@kernel.org> From: Suzuki K Poulose Message-ID: Date: Tue, 23 Mar 2021 17:05:26 +0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.16; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <161651726490.2050093.5536833570808361940.b4-ty@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/03/2021 16:34, Marc Zyngier wrote: > On Tue, 23 Mar 2021 12:06:28 +0000, Suzuki K Poulose wrote: >> This series enables future IP trace features Embedded Trace Extension >> (ETE) and Trace Buffer Extension (TRBE). This series applies on >> v5.12-rc4 + some patches queued. A standalone tree is also available here [0]. >> The queued patches (almost there) are included in this posting for >> the sake of constructing a tree from the posting. >> >> ETE is the PE (CPU) trace unit for CPUs, implementing future >> architecture extensions. ETE overlaps with the ETMv4 architecture, with >> additions to support the newer architecture features and some restrictions >> on the supported features w.r.t ETMv4. The ETE support is added by extending >> the ETMv4 driver to recognise the ETE and handle the features as exposed by >> the TRCIDRx registers. ETE only supports system instructions access from the >> host CPU. The ETE could be integrated with a TRBE (see below), or with >> the legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same >> firmware description as the ETMs and requires a node per instance. >> >> [...] > > Applied to fixes, thanks! > > [01/19] kvm: arm64: Hide system instruction access to Trace registers > commit: 4af0afe252a2701732c317585f7c3ef6596b8f3d > Thanks Marc !