From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Liankun Yang <liankun.yang@mediatek.com>,
chunkuang.hu@kernel.org, p.zabel@pengutronix.de,
airlied@gmail.com, simona@ffwll.ch, matthias.bgg@gmail.com,
jitao.shi@mediatek.com, mac.shen@mediatek.com,
peng.liu@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/1] drm/mediatek: Adjust bandwidth limit for DP
Date: Wed, 16 Apr 2025 10:42:16 +0200 [thread overview]
Message-ID: <bd60aae8-2df3-45d7-9db6-9d21d15a079c@collabora.com> (raw)
In-Reply-To: <20250318140236.13650-2-liankun.yang@mediatek.com>
Il 18/03/25 15:02, Liankun Yang ha scritto:
> By adjusting the order of link training and relocating it to HPD,
> link training can identify the usability of each lane in the current link.
>
> It also supports handling signal instability and weakness due to
> environmental issues, enabling the acquisition of a stable bandwidth
> for the current link. Subsequently, DP work can proceed based on
> the actual maximum bandwidth.
>
> It should training in the hpd event thread.
> Check the mode with lane count and link rate of training.
>
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
This patch still breaks the internal eDP display on MT8195 Tomato,
but DP is fine.
Please test your patches on that machine before sending again.
Regards,
Angelo
> ---
> Change in V3:
> - Remove 'mtk_dp->enabled = false" in atomic disable.
> - Remove 'mtk_dp->enabled = true" in atomic enable.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20241025083036.8829-4-liankun.yang@mediatek.com/
>
> Change in V2:
> - Adjust DP training timing.
> - Adjust parse capabilities timing.
> - Add power on/off for connect/disconnect.
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240315015233.2023-1-liankun.yang@mediatek.com/
> ---
> drivers/gpu/drm/mediatek/mtk_dp.c | 39 ++++++++++++++++---------------
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 3d4648d2e15f..fb76fc1bf497 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -1976,6 +1976,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
> struct mtk_dp *mtk_dp = dev;
> unsigned long flags;
> u32 status;
> + int ret;
>
> if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
> msleep(100);
> @@ -1994,9 +1995,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
> memset(&mtk_dp->info.audio_cur_cfg, 0,
> sizeof(mtk_dp->info.audio_cur_cfg));
>
> + mtk_dp->enabled = false;
> + /* power off aux */
> + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> + DP_PWR_STATE_BANDGAP_TPLL,
> + DP_PWR_STATE_MASK);
> +
> mtk_dp->need_debounce = false;
> mod_timer(&mtk_dp->debounce_timer,
> jiffies + msecs_to_jiffies(100) - 1);
> + } else {
> + mtk_dp_aux_panel_poweron(mtk_dp, true);
> +
> + ret = mtk_dp_parse_capabilities(mtk_dp);
> + if (ret)
> + drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> +
> + /* Training */
> + ret = mtk_dp_training(mtk_dp);
> + if (ret)
> + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> +
> + mtk_dp->enabled = true;
> }
> }
>
> @@ -2162,16 +2182,6 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,
>
> drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
>
> - /*
> - * Parse capability here to let atomic_get_input_bus_fmts and
> - * mode_valid use the capability to calculate sink bitrates.
> - */
> - if (mtk_dp_parse_capabilities(mtk_dp)) {
> - drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> - drm_edid_free(drm_edid);
> - drm_edid = NULL;
> - }
> -
> if (drm_edid) {
> /*
> * FIXME: get rid of drm_edid_raw()
> @@ -2365,13 +2375,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
>
> mtk_dp_aux_panel_poweron(mtk_dp, true);
>
> - /* Training */
> - ret = mtk_dp_training(mtk_dp);
> - if (ret) {
> - drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> - goto power_off_aux;
> - }
> -
> ret = mtk_dp_video_config(mtk_dp);
> if (ret)
> goto power_off_aux;
> @@ -2389,7 +2392,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
> sizeof(mtk_dp->info.audio_cur_cfg));
> }
>
> - mtk_dp->enabled = true;
> mtk_dp_update_plugged_status(mtk_dp);
>
> return;
> @@ -2404,7 +2406,6 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge,
> {
> struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
>
> - mtk_dp->enabled = false;
> mtk_dp_update_plugged_status(mtk_dp);
> mtk_dp_video_enable(mtk_dp, false);
> mtk_dp_audio_mute(mtk_dp, true);
prev parent reply other threads:[~2025-04-16 8:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-18 14:02 [PATCH v3 0/1] *** SUBJECT HERE *** Liankun Yang
2025-03-18 14:02 ` [PATCH v3 1/1] drm/mediatek: Adjust bandwidth limit for DP Liankun Yang
2025-04-16 8:42 ` AngeloGioacchino Del Regno [this message]
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