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Sun, 25 Oct 2026 17:32:12 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:da43:aeff:fecc:bfd5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3adebaddd45sm4618312a91.2.2026.10.25.17.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Oct 2026 17:32:11 -0700 (PDT) Sender: Guenter Roeck Date: Sun, 25 Oct 2026 17:32:10 -0700 From: Guenter Roeck To: Remy Demangeot Cc: Jonathan Corbet , Shuah Khan , Randy Dunlap , Eugene Shalygin , linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwmon: (asus-ec-sensors) add MAXIMUS IX EXTREME Message-ID: References: <20261015-b4-m9e-extreme-v1-1-621da921e320@demangeot.net> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261015-b4-m9e-extreme-v1-1-621da921e320@demangeot.net> On Thu, Oct 15, 2026 at 06:09:31PM +0200, Remy Demangeot wrote: > From: Remy Demangeot > > Add support for the ROG MAXIMUS IX EXTREME (Intel Z270). The board > uses the same EC layout as the PRIME Z270-A for the chipset and > T_Sensor temperatures, and additionally exposes the VRM temperature > at the same register as the 300-series boards (bank 0, 0x3e), so add > that sensor to the Intel 200-series family. > > The hardware access mutex is \_SB_.PCI0.LPCB.SIO1.MUT0, as on the > PRIME Z270-A (verified in the board's DSDT). > > Readings were checked against HWiNFO 8.54 on the same machine > (Chipset 47 C, T_Sensor 25 C, VRM 32 C). > > Signed-off-by: Remy Demangeot Applied. > --- > The board's EC also exposes more sensors that HWiNFO reads, but they > need access patterns the driver does not have yet: > - three extension card fans (EXT_FAN1-3): write 0x0a/0x0b/0x0c to > bank 0 register 0x43 (selector), then read 0x57:0x58 (BE RPM); > - EXT_Sensor1-3 temperatures at bank 0, 0x60-0x62; > - Water_In/Out and Water_In2/Out2 on a second EC (firmware ID > "RGE2-Z270-0109") at I/O ports 0x68/0x6c, bank 1, registers > 0x0d/0x0b/0x13/0x11 (same offsets as Water_In/Out on AMD boards). > > I have a working out-of-tree driver for these and can prepare follow-up > patches if this approach would be acceptable. I am curions - any reason to assume that it would _not_ be acceptable ? Thanks, Guenter