From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C082DFA3743 for ; Tue, 1 Nov 2022 11:51:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbiKALvO (ORCPT ); Tue, 1 Nov 2022 07:51:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231500AbiKALuo (ORCPT ); Tue, 1 Nov 2022 07:50:44 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E62B71B1 for ; Tue, 1 Nov 2022 04:48:10 -0700 (PDT) Received: from kwepemi500012.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4N1p8h5wdvzpVTF; Tue, 1 Nov 2022 19:44:36 +0800 (CST) Received: from [10.67.110.176] (10.67.110.176) by kwepemi500012.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 1 Nov 2022 19:48:08 +0800 Subject: Re: [PATCH] x86/cpu: fix undefined behavior in bit shift for intel_detect_tlb To: Peter Zijlstra CC: , , , , , , , , , , , , References: <20221031114340.4185587-1-cuigaosheng1@huawei.com> From: cuigaosheng Message-ID: Date: Tue, 1 Nov 2022 19:48:07 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.110.176] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemi500012.china.huawei.com (7.221.188.12) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We don't need to add UBSAN calltrace, so I have merged the patch with another patch("x86/cpu: replacing the open-coded shift with BIT(x)"), please ignore this patch,thanks for review this patch! On 2022/10/31 20:32, Peter Zijlstra wrote: > On Mon, Oct 31, 2022 at 01:30:57PM +0100, Peter Zijlstra wrote: >> On Mon, Oct 31, 2022 at 07:43:40PM +0800, Gaosheng Cui wrote: >>> Shifting signed 32-bit value by 31 bits is undefined, so changing >>> significant bit to unsigned. The UBSAN warning calltrace like below: >>> >>> UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/intel.c:948:21 >>> left shift of 1 by 31 places cannot be represented in type 'int' >> Is it really? Shouldn't -fstrict-overflow define this case? > -fno-strict-overflow that is, which implies -fwrapv which ensures 2s > complement, at which point shifting signed numbers is fully defined. > > .