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Tue, 11 Nov 2025 08:31:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEK0C7zoIdCCrbSGtOR2lA7hiOGv0VrSOdA1mvOcJK1ts7OjzqJ7ukZDrIrLaxwld0WkX5Shw== X-Received: by 2002:a17:90b:3a91:b0:33e:2d0f:479b with SMTP id 98e67ed59e1d1-3436cb7bcfcmr16607120a91.6.1762878664213; Tue, 11 Nov 2025 08:31:04 -0800 (PST) Received: from [10.216.22.22] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-343685301f8sm11854378a91.5.2025.11.11.08.30.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 08:31:03 -0800 (PST) Message-ID: Date: Tue, 11 Nov 2025 22:00:51 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH v17 03/12] power: reset: reboot-mode: Add support for 64 bit magic Content-Language: en-US To: Bjorn Andersson Cc: Mukesh Ojha , Bartosz Golaszewski , Sebastian Reichel , Rob Herring , Sudeep Holla , Souvik Chakravarty , Krzysztof Kozlowski , Conor Dooley , Andy Yan , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Vinod Koul , Catalin Marinas , Will Deacon , Florian Fainelli , Moritz Fischer , John Stultz , Matthias Brugger , Krzysztof Kozlowski , Dmitry Baryshkov , Stephen Boyd , Andre Draszik , Kathiravan Thirumoorthy , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Elliot Berman , Xin Liu , Srinivas Kandagatla , Umang Chheda , Nirmesh Kumar Singh References: <20251109-arm-psci-system_reset2-vendor-reboots-v17-0-46e085bca4cc@oss.qualcomm.com> <20251109-arm-psci-system_reset2-vendor-reboots-v17-3-46e085bca4cc@oss.qualcomm.com> <20251110134529.uljjqzb3vhda3vya@hu-mojha-hyd.qualcomm.com> <681a72ba-d8fb-bfc2-d2bb-d80ac667bc5c@oss.qualcomm.com> <5c83c9a1-e123-95bb-1434-588ee8c52b25@oss.qualcomm.com> From: Shivendra Pratap In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTExMDEzMiBTYWx0ZWRfX8CGD09RZHOhL RqodXReeL6NliLNiAVxdvdL1FhSvtTlRBFlXNqzg086k40JoNwT+a00Zy4eNnIs9bQ1ezko2rgr PellbOb7rmc1qYps+s8Of8phb7oQvBOREQSrINfyf+nUlZFos38Cn52a6kuqv74+ekA1hRktAlw mLFlya8U+w3LhQ6Hqbbu8Mq6e8ZUOL5mwAY3SAJzmDyYdyaiJ6DGiS0ao3zBkReUBjemZ8pN2cU Dy4sZtWtkP5AjZltagyb+61HjhR50HZzjaU/P4BgTNh2r4hELW9Se+qVKckdypXl+ckhFmLGM25 l1iJh70szWsCEMSwiJ3fn3FMJp/7S6d1nfY+w/ktLtZA/eXy+LIGR3A+OicmlRceH4Gqonvj0jW yHFShKTV5vhba20gP0XHYGNVMSKN3g== X-Authority-Analysis: v=2.4 cv=CsKys34D c=1 sm=1 tr=0 ts=691364c9 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=5lduEm2px6IFDn4QHGYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: 1c18IEFQkaLlH6ukBARy0iJPfdT9nwkx X-Proofpoint-GUID: 1c18IEFQkaLlH6ukBARy0iJPfdT9nwkx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-11_03,2025-11-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511110132 On 11/11/2025 9:55 PM, Bjorn Andersson wrote: > On Tue, Nov 11, 2025 at 08:20:43PM +0530, Shivendra Pratap wrote: >> >> >> On 11/11/2025 12:03 AM, Bjorn Andersson wrote: >>> On Mon, Nov 10, 2025 at 11:22:40PM +0530, Shivendra Pratap wrote: >>>> >>>> >>>> On 11/10/2025 10:00 PM, Bjorn Andersson wrote: >>>>> On Mon, Nov 10, 2025 at 07:15:29PM +0530, Mukesh Ojha wrote: >>>>>> On Sun, Nov 09, 2025 at 08:07:16PM +0530, Shivendra Pratap wrote: >>>>>>> Current reboot-mode supports a single 32-bit argument for any >>>>>>> supported mode. Some reboot-mode based drivers may require >>>>>>> passing two independent 32-bit arguments during a reboot >>>>>>> sequence, for uses-cases, where a mode requires an additional >>>>>>> argument. Such drivers may not be able to use the reboot-mode >>>>>>> driver. For example, ARM PSCI vendor-specific resets, need two >>>>>>> arguments for its operation – reset_type and cookie, to complete >>>>>>> the reset operation. If a driver wants to implement this >>>>>>> firmware-based reset, it cannot use reboot-mode framework. >>>>>>> >>>>>>> Introduce 64-bit magic values in reboot-mode driver to >>>>>>> accommodate dual 32-bit arguments when specified via device tree. >>>>>>> In cases, where no second argument is passed from device tree, >>>>>>> keep the upper 32-bit of magic un-changed(0) to maintain backward >>>>>>> compatibility. >>>>>>> >>>>>>> Update the current drivers using reboot-mode for a 64-bit magic >>>>>>> value. >>>> >>>> [SNIP..] >>>> >>>>>>> + if (magic > U32_MAX) >>>>>>> + return -EINVAL; >>>>>>> + >>>>>>> + magic_32 = magic; >>>>>>> + >>>>>>> syscon_rbm = container_of(reboot, struct syscon_reboot_mode, reboot); >>>>>>> >>>>>>> ret = regmap_update_bits(syscon_rbm->map, syscon_rbm->offset, >>>>>>> - syscon_rbm->mask, magic); >>>>>>> + syscon_rbm->mask, magic_32); >>>>> >>>>> As above, if we're no longer silently discarding bits, I think we should >>>>> compare the magic against syscon_rbm->mask. >>>>> >>>>> No need for a local variable, just type cast after checking the validity. >>>> >>>> Trying to summarize below why we added these check- >>>> >>>> the patch in v11 used typecasting and did not have any of these checks(link below): >>>> https://lore.kernel.org/all/20250717-arm-psci-system_reset2-vendor-reboots-v11-2-df3e2b2183c3@oss.qualcomm.com/ >>>> >>>> As per below upstream review, type cast was removed and bound checks were added all-over patchset: >>>> "As a general rule of thumb, code with casts is poor quality code. Try >>>> to write the code without casts." - >>>> https://lore.kernel.org/all/8d4a42b6-657f-4c30-8e25-4213d8d53a89@lunn.ch/ >>>> >>>> We can revert to the typecast way. Please suggest. >>>> >>> >>> Okay, I'm okay with Andrew's original request, stick to that for the >>> nvmem case. Although I don't fancy the name "magic_32", and would prefer >>> that you just call it "value" or something. >> >> sure will make it proper wherever applicable. >> >>> >>> >>> For pon and syscon however, I'm wondering why you have ignored Andrew's >>> other request from that same email: >>> >>> """ >>> You might be able to go further, and validate that magic actually fits >>> into the field when you consider the << pon->reason_shift. >>> """ >>> >>> Writing "if (magic > U32_MAX)" in a snippet of code where magic isn't >>> allowed to be more than either 32 or 64 is misleading. >>> >>> For syscon, it's true that the parameter is an unsigned long, but the >>> actual limit better be based on syscon_rbm->mask. >> >> May be i was not able to interpret it correctly. Basically tried to >> make sure that magic that now coming in a "u64 magic" should be passed >> ahead only it its a 32 bit value. >> > > That is the correct interpretation of the original ask. But what I'm > saying is that if you write: > > if (magic > U32_MAX) > > then that means "check that magic isn't larger than 32 bits". So the > reader will see that and understand that magic can only be 32 bits. > > But the actual PON magic value is 5 or 6 bits, not 32 - so you should > check that the value fits in 5 or 6 bits. sure. thanks. > >> So should i get rid of the checks done here for syscon and pon? >> > > Continuing to silently ignoring other bits would be one option, but > you've been asked to sanity check the values, so please do that. You > have the code, just compare with the correct value. ok. got it. thanks. thanks, Shivendra