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Tue, 15 Sep 2026 09:38:45 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v5 11/15] iommu/arm-smmu-v3: Discard partial PRI faults on PRIQ overflow Date: Tue, 15 Sep 2026 09:38:23 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A800:EE_|SA3PR12MB7973:EE_ X-MS-Office365-Filtering-Correlation-Id: e3b606cc-5386-48ad-9e62-08df1347e213 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|23010399003|82310400026|1800799024|10067099003|56012099006|11063799006|5023799004|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jncHosaWf2ju825UfrJw0MyAg8PETTOnR3TDhC8q6u05vGPsY7K5U4CySAXciKwavr/JGDhpVPU9/7KQWOZCwJPyoHveuJp3RY5uqGg9zXgc+z1nZwiw13eEagauMwIIX/f6xKRnCLTKRN7ExqLHQ/DB9gFUvxUDi6R3AUcp/+Y6G3TvZwhd70z3w9Pz4FopdmW3uy7yOhCrRGh7sRr4ZCXFAcVY2G2CyWlzV2wvT9tvNJw2Hnl9waMlP98jcBXOA7jcCo8qszvTOMxCvu1eSs/nywg6sJWQCmyhuPBQnKMtRhcylYT8Cd0JmHEi9mPlTZoIw80i1qH85HKQ47/pLjYnvtdvYHIE5GtyI3YhosGzZGqJx8KCRLFo7ihjPUZHX5tHXCIWJ+AciHp75xT4HskO/d9N5WPr9+rJrVhy6jP7t5a0slzeKSaQunC1b/cl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 16:39:16.4666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3b606cc-5386-48ad-9e62-08df1347e213 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A800.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7973 On PRIQ overflow, partial requests stored via report_partial_fault() whose LAST-page entry was lost stay in iopf_param->partial. Drop them by calling iopf_queue_discard_partial(), matching intel-iommu's handling. Do it only after the queue is fully drained, since the visible entries all precede the loss point: a group whose LAST-page entry is still in the queue gets assembled before the discard, rather than losing its stored partials to it. Nothing can arrive in between, as an active overflow inhibits new entries from being written to the PRI queue until a final CONS write acknowledges it (IHI0070 8.1). Suggested-by: Harsha Vardhan V Reviewed-by: Jonathan Cameron Assisted-by: LLM Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 17ca3fcd1b9c0..7c9b3bcdbf17e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2454,15 +2454,27 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) struct arm_smmu_queue *q = &smmu->priq.q; struct arm_smmu_ll_queue *llq = &q->llq; u64 evt[PRIQ_ENT_DWORDS]; + bool overflow = false; do { while (!queue_remove_raw(q, evt)) arm_smmu_handle_ppr(smmu, evt); - if (queue_sync_prod_in(q) == -EOVERFLOW) + if (queue_sync_prod_in(q) == -EOVERFLOW) { dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + overflow = true; + } } while (!queue_empty(llq)); + /* + * Discard the partial faults after the drain, so any group with its + * LAST-page entry visible in the queue gets assembled beforehand. An + * active overflow condition inhibits new entries from being written + * to the PRI queue, until it gets acknowledged below. + */ + if (overflow) + iopf_queue_discard_partial(smmu->evtq.iopf); + /* Sync our overflow flag, as we believe we're up to speed */ queue_sync_cons_ovf(q); return IRQ_HANDLED; -- 2.43.0