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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Pd6OAaJRdymymuGlgK0KLuwUSeu9WrFbm8L1r4JaAqFwZqfWU4tRFR0H74SY0OfcJx3a8o1ruptqsXI4qpKGQI3e+Gn58C+MYbaiXnpdiaQF9cCV3N1BeJcrgSLb2nh+G4A0A1m2v84iyNggDFnj/MGN5BnYmM++eeFsQQqYKtixLJqCHE4zdaV8rrWwn9OkJux24BToEEXk6c5eJI9yq/K3nj7neKSE9BnvmREKsfAFLY2n35WYBaTtMinLlv980XhnmkgYs7BCuWYlPqSv8b/G/QQH5wfNR4MG7jlpxVRbSdZSUOJzO2mihi3WUk4qMwDsQIrqF4yFAuaXbbWwjCX25WDujFlQSXF+aeuiLfDA8nTpxyErJwIHlKb9j1Q6mZBYijrEZMKZT4TT5jz9V7wW/5WPRs5zzwo9Jc62pM2pUVrGyWXsOdShwbT0oW8O X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 01:41:55.3573 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51d6f99c-dbeb-488a-abf7-08dea1a2aac3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6735.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8311 On AMD systems, the existing MBA feature allows the user to set a bandwidth limit for each QoS domain. However, multiple QoS domains share system memory bandwidth as a resource. In order to ensure that system memory bandwidth is not over-utilized, the user must statically partition the available system bandwidth between the active QoS domains. Active domains are those that have at least one thread running in them. If a QoS domain is not active, its bandwidth allocation is not used by any thread and is effectively wasted. On the other hand, if a QoS domain is active but its bandwidth allocation is too low, threads running in that domain may not be able to utilize the full potential of the system memory bandwidth. This typically results in system memory being under-utilized since not all QoS domains are using their full bandwidth allocation. AMD PQoS Global Bandwidth Enforcement (GLBE) provides a mechanism for software to specify bandwidth limits for groups of threads that span multiple QoS domains. This collection of QoS domains is referred to as a GLBE control domain. The GLBE ceiling sets a maximum limit on memory bandwidth in GLBE control domain. Bandwidth is shared by all threads in a Class of Service (COS) across every QoS domain managed by the GLBE control domain. The GLBE control domain is configurable using the BIOS setup utility. By default the GLBE control domain is aligned to system NPS (Nodes Per Socket) configuration. NPS is a BIOS-level setting on AMD processors that determines how many NUMA (Non Uniform Memory Access) nodes each CPU socket is divided into. NPS allows administrators to tune memory locality, bandwidth, and latency for different workloads. GLBE support is reported through CPUID.8000_0020_EBX_x0[GLBE] (bit 7). When this bit is set to 1, the platform supports GLBE. Since the AMD Memory Bandwidth Enforcement feature is represented as MBA, the Global Bandwidth Enforcement feature will be shown as GMBA to maintain consistent naming. Add GMBA support to resctrl and introduce a kernel parameter that allows enabling or disabling the feature at boot time. The GLBE feature details are documented in: AMD64 Zen6 Platform Quality of Service (PQOS) Extensions: Publication # 69193 Revision: 1.00, Issue Date: March 2026 available at https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- v2: Updated the commit message to include more details about active QoS domains. Updated the commit message to clarify that the GLBE control domain is configurable using the BIOS setup utility is aligned to NPS. Added link to the PQOS spec. --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/scattered.c | 1 + 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index cf3807641d89..f23cad453f17 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6452,7 +6452,7 @@ Kernel parameters rdt= [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec, abmc, sdciae, energy[:guid], + mba, gmba, smba, bmec, abmc, sdciae, energy[:guid], perf[:guid]. E.g. to turn on cmt and turn off mba use: rdt=cmt,!mba diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 1d506e5d6f46..356f7a11d47c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -508,7 +508,6 @@ #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Counters */ #define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions */ #define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */ - #define X86_FEATURE_SDCIAE (21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */ #define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /* * Clear CPU buffers before VM-Enter if the vCPU @@ -516,6 +515,7 @@ * and purposes if CLEAR_CPU_BUF_VM is set). */ #define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */ +#define X86_FEATURE_GMBA (21*32+21) /* Global Memory Bandwidth Allocation */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 7667cf7c4e94..269265d98ad7 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -795,6 +795,7 @@ enum { RDT_FLAG_L2_CAT, RDT_FLAG_L2_CDP, RDT_FLAG_MBA, + RDT_FLAG_GMBA, RDT_FLAG_SMBA, RDT_FLAG_BMEC, RDT_FLAG_ABMC, @@ -822,6 +823,7 @@ static struct rdt_options rdt_options[] __ro_after_init = { RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), + RDT_OPT(RDT_FLAG_GMBA, "gmba", X86_FEATURE_GMBA), RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC), diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 837d6a4b0c28..077cf452c257 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -60,6 +60,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 }, { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, + { X86_FEATURE_GMBA, CPUID_EBX, 7, 0x80000020, 0 }, { X86_FEATURE_TSA_SQ_NO, CPUID_ECX, 1, 0x80000021, 0 }, { X86_FEATURE_TSA_L1_NO, CPUID_ECX, 2, 0x80000021, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, -- 2.43.0